[llvm] 1540ed5 - [AArch64] Neoverse V2 FeatureDisableLatencySchedHeuristic (#140897)

[via llvm-commits]

Author: Sjoerd Meijer
Date: 2025-06-06T13:25:17+01:00
New Revision: 1540ed52eeb25d6cf8142c1071d85a50f5c167b1

URL: https://github.com/llvm/llvm-project/commit/1540ed52eeb25d6cf8142c1071d85a50f5c167b1
DIFF: https://github.com/llvm/llvm-project/commit/1540ed52eeb25d6cf8142c1071d85a50f5c167b1.diff

LOG: [AArch64] Neoverse V2 FeatureDisableLatencySchedHeuristic (#140897)

This adds FeatureDisableLatencySchedHeuristic to the Neoverse V2 core
tuning description. This gives us a 20% improvement on a key workload,
some other minor improvements here and there, and no real regressions;
nothing outside the noise levels.

Earlier attempts to solve this problems included disabling the MI
scheduler entirely (#127784), and #139557 was about a heuristic to not
schedule hand-written vector code. This solution is preferred because it
avoids another heuristic and achieves what we want, and for what is
worth, there is a lot of precedent for setting this feature.

Thanks to:
- Ricardo Jesus for pointing out this subtarget feature, and
- Cameron McInally for the extensive performance testing.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64Processors.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index a5f0f6a2eb150..e7a3527202f6a 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -561,7 +561,8 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2
                                       FeatureEnableSelectOptimize,
                                       FeatureUseFixedOverScalableIfEqualCost,
                                       FeatureAvoidLDAPUR,
-                                      FeaturePredictableSelectIsExpensive]>;
+                                      FeaturePredictableSelectIsExpensive,
+                                      FeatureDisableLatencySchedHeuristic]>;
 
 def TuneNeoverseV3 : SubtargetFeature<"neoversev3", "ARMProcFamily", "NeoverseV3",
                                       "Neoverse V3 ARM processors", [