[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)
Janek van Oirschot via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 6 04:23:42 PDT 2025
================
@@ -2388,30 +2388,25 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
} // end True16Predicate = NotHasTrue16BitInsts
let True16Predicate = UseRealTrue16Insts in {
-def : GCNPat <
- (rotr i32:$src0, i32:$src1),
- (V_ALIGNBIT_B32_t16_e64 /* src0_modifiers */ 0, $src0,
- /* src1_modifiers */ 0, $src0,
- /* src2_modifiers */ 0,
- (EXTRACT_SUBREG $src1, lo16),
- /* clamp */ 0, /* op_sel */ 0)
->;
-
-def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
- (V_ALIGNBIT_B32_t16_e64 0, /* src0_modifiers */
- (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
- 0, /* src1_modifiers */
- (i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
- 0, /* src2_modifiers */
- (i16 (EXTRACT_SUBREG VGPR_32:$src1, lo16)),
- /* clamp */ 0, /* op_sel */ 0)>;
+ def : GCNPat<(rotr i32:$src0, i32:$src1),
+ (V_ALIGNBIT_B32_t16_e64 /* src0_modifiers */ 0, $src0,
+ /* src1_modifiers */ 0, $src0,
+ /* src2_modifiers */ 0, (EXTRACT_SUBREG $src1, lo16),
+ /* clamp */ 0, /* op_sel */ 0)>;
----------------
JanekvO wrote:
What's changed? I think it'd be best to move any drive-by format fixes in a separate patch
https://github.com/llvm/llvm-project/pull/140694
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