[llvm] [NFC][VectorCombine] Add tests for narrow bitcast of shuffle (PR #143085)

via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 6 00:10:33 PDT 2025 

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-transforms

Author: hanbeom (ParkHanbum)

<details>
<summary>Changes</summary>

Previous TODO had a test for Narrow bitcast. However, this test is an issue that has already been patched and resolved. What remains is a negative test case that is purposely not optimized, so TODO should be removed.

However, some transformations have dependence on the InstCombine Pass; we can track the source of each element of ShuffleVector to optimize it, so we not need to have dependency with InstCombine leave tests as TODO to test.

Proof: https://alive2.llvm.org/ce/z/YJMgyR

---
Full diff: https://github.com/llvm/llvm-project/pull/143085.diff


2 Files Affected:

- (modified) llvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll (-3) 
- (added) llvm/test/Transforms/VectorCombine/shuffle-bitcast.ll (+94) 


``````````diff
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll b/llvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll
index 9b03433e00cbc..d7422ff718f72 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll
@@ -243,7 +243,6 @@ define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_can_be_converted_up(<8 x i16>
 }
 
 ; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<16 x i8>(v)))
-; TODO: Narrow and squash shuffles?
 
 define <4 x i32> @shuffle_8_bitcast_32_shuffle_32_can_not_be_converted_up(<16 x i8> %v1) {
 ; CHECK-LABEL: @shuffle_8_bitcast_32_shuffle_32_can_not_be_converted_up(
@@ -259,7 +258,6 @@ define <4 x i32> @shuffle_8_bitcast_32_shuffle_32_can_not_be_converted_up(<16 x
 }
 
 ; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<8 x i16>(v)))
-; TODO: Narrow and squash shuffles?
 
 define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_can_not_be_converted_up(<8 x i16> %v1) {
 ; CHECK-LABEL: @shuffle_16_bitcast_32_shuffle_32_can_not_be_converted_up(
@@ -289,7 +287,6 @@ define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_can__be_converted_up(<16 x i8>
 }
 
 ; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<16 x i8>(v)))
-; TODO: Narrow and squash shuffles?
 
 define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_can_not_be_converted_up(<16 x i8> %v1) {
 ; CHECK-LABEL: @shuffle_8_bitcast_16_shuffle_16_can_not_be_converted_up(
diff --git a/llvm/test/Transforms/VectorCombine/shuffle-bitcast.ll b/llvm/test/Transforms/VectorCombine/shuffle-bitcast.ll
new file mode 100644
index 0000000000000..4585a38e0b70d
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/shuffle-bitcast.ll
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -S -p vector-combine | FileCheck %s
+
+; TODO: Narrow and squash shuffles
+
+; TODO: We can reduce to ret bitcast <16 x i8> %v1 to <8 x i16>
+define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_should_identity(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_should_identity(
+; CHECK-SAME: <16 x i8> [[V1:%.*]], <16 x i8> [[V2:%.*]]) {
+; CHECK-NEXT:    [[SHUFFLE1:%.*]] = shufflevector <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <8 x i16>
+; CHECK-NEXT:    [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> poison, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    ret <8 x i16> [[SHUFFLE2]]
+;
+  %shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  %bc1 = bitcast <16 x i8> %shuffle1 to <8 x i16>
+  %shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> poison, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i16> %shuffle2
+}
+
+; TODO: Can be reduced to shuffle for %v1
+define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_should_identity_not_ordered(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_should_identity_not_ordered(
+; CHECK-SAME: <16 x i8> [[V1:%.*]], <16 x i8> [[V2:%.*]]) {
+; CHECK-NEXT:    [[SHUFFLE1:%.*]] = shufflevector <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <8 x i16>
+; CHECK-NEXT:    [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> poison, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
+; CHECK-NEXT:    ret <8 x i16> [[SHUFFLE2]]
+;
+  %shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  %bc1 = bitcast <16 x i8> %shuffle1 to <8 x i16>
+  %shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> poison, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
+  ret <8 x i16> %shuffle2
+}
+
+; TODO: We can reduce to ret bitcast <8 x i16> %v1 to <4 x i32>
+define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_identity(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_identity(
+; CHECK-SAME: <8 x i16> [[V1:%.*]], <8 x i16> [[V2:%.*]]) {
+; CHECK-NEXT:    [[SHUFFLE1:%.*]] = shufflevector <8 x i16> [[V1]], <8 x i16> [[V2]], <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <8 x i16> [[SHUFFLE1]] to <4 x i32>
+; CHECK-NEXT:    [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 0, i32 1>
+; CHECK-NEXT:    ret <4 x i32> [[SHUFFLE2]]
+;
+  %shuffle1 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
+  %bc1 = bitcast <8 x i16> %shuffle1 to <4 x i32>
+  %shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 0, i32 1>
+  ret <4 x i32> %shuffle2
+}
+
+; TODO: Can be reduced to shuffle for %v1
+define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_identity_not_ordered(<8 x i16> %v1, <8 x i16> %v2) {
+; CHECK-LABEL: define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_identity_not_ordered(
+; CHECK-SAME: <8 x i16> [[V1:%.*]], <8 x i16> [[V2:%.*]]) {
+; CHECK-NEXT:    [[SHUFFLE1:%.*]] = shufflevector <8 x i16> [[V1]], <8 x i16> [[V2]], <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <8 x i16> [[SHUFFLE1]] to <4 x i32>
+; CHECK-NEXT:    [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
+; CHECK-NEXT:    ret <4 x i32> [[SHUFFLE2]]
+;
+  %shuffle1 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
+  %bc1 = bitcast <8 x i16> %shuffle1 to <4 x i32>
+  %shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
+  ret <4 x i32> %shuffle2
+}
+
+; TODO: We can reduce to ret bitcast <16 x i8> %v1 to <8 x i16>
+define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_identity_ordered(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_identity_ordered(
+; CHECK-SAME: <16 x i8> [[V1:%.*]], <16 x i8> [[V2:%.*]]) {
+; CHECK-NEXT:    [[SHUFFLE1:%.*]] = shufflevector <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <8 x i16>
+; CHECK-NEXT:    [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> poison, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    ret <8 x i16> [[SHUFFLE2]]
+;
+  %shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  %bc1 = bitcast <16 x i8> %shuffle1 to <8 x i16>
+  %shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> poison, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i16> %shuffle2
+}
+
+; TODO: Can be reduced to shuffle for %v1
+define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_identity_not_ordered(<16 x i8> %v1, <16 x i8> %v2) {
+; CHECK-LABEL: define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_identity_not_ordered(
+; CHECK-SAME: <16 x i8> [[V1:%.*]], <16 x i8> [[V2:%.*]]) {
+; CHECK-NEXT:    [[SHUFFLE1:%.*]] = shufflevector <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <8 x i16>
+; CHECK-NEXT:    [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> poison, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
+; CHECK-NEXT:    ret <8 x i16> [[SHUFFLE2]]
+;
+  %shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  %bc1 = bitcast <16 x i8> %shuffle1 to <8 x i16>
+  %shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> poison, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
+  ret <8 x i16> %shuffle2
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/143085

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