[llvm] [NVPTX] Use cvt.sat to lower min/max clamping to i8 and i16 ranges (PR #143016)

[Artem Belevich via llvm-commits]

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@@ -5667,6 +5677,49 @@ static SDValue combineADDRSPACECAST(SDNode *N,
   return SDValue();
 }
 
+static SDValue combineMINMAX(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
+
+  EVT VT = N->getValueType(0);
+  if (!(VT == MVT::i32 || VT == MVT::i64 || VT == MVT::i16))
+    return SDValue();
+
+  SDValue Val;
+  APInt Ceil, Floor;
+  if (!(sd_match(N, m_SMin(m_SMax(m_Value(Val), m_ConstInt(Floor)),
+                           m_ConstInt(Ceil))) ||
+        sd_match(N, m_SMax(m_SMin(m_Value(Val), m_ConstInt(Ceil)),
+                           m_ConstInt(Floor)))))
+    return SDValue();
+
+  const unsigned BitWidth = VT.getSizeInBits();
+  SDLoc DL(N);
+  auto MatchTuncSat = [&](MVT DestVT) {
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Artem-B wrote:

Nit: Perhaps rename `MatchTruncSat` to `TryToLowerAsSaturatedConversion` as we're not just matching the graph nodes, but also constructing their replacement.

https://github.com/llvm/llvm-project/pull/143016