[llvm] [PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (PR #142220)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 5 08:20:02 PDT 2025
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/142220
>From d603015f54da0ea199260d314df67ed00e143a64 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 30 May 2025 11:15:07 -0500
Subject: [PATCH 1/4] clean up code gen for register mapping used in stxvp
spilling
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 109 ++++++++++++++------
1 file changed, 77 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 45183af0b7984..336f84c9002f0 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1238,41 +1238,50 @@ static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
#endif
}
+#if 0
static void spillRegPairs(MachineBasicBlock &MBB,
MachineBasicBlock::iterator II, DebugLoc DL,
const TargetInstrInfo &TII, Register SrcReg,
- unsigned FrameIndex, bool IsLittleEndian,
- bool IsKilled, bool TwoPairs) {
- unsigned Offset = 0;
+ unsigned FrameIndex, bool IsLittleEndian) {
+ MachineInstr &MI = *II;
+ bool IsKilled = MI.getOperand(0).isKill();
+ unsigned Offset = IsLittleEndian ? 48 : 0;
+
// The register arithmetic in this function does not support virtual
// registers.
+ /*
assert(!SrcReg.isVirtual() &&
"Spilling register pairs does not support virtual registers.");
+ */
- if (TwoPairs)
- Offset = IsLittleEndian ? 48 : 0;
- else
- Offset = IsLittleEndian ? 16 : 0;
- Register Reg = (SrcReg > PPC::VSRp15) ? PPC::V0 + (SrcReg - PPC::VSRp16) * 2
- : PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(Reg, getKillRegState(IsKilled)),
- FrameIndex, Offset);
+ Register RegP0 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0);
+ Register RegP1 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(Reg + 1, getKillRegState(IsKilled)),
- FrameIndex, Offset);
- if (TwoPairs) {
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(Reg + 2, getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(Reg + 3, getKillRegState(IsKilled)),
- FrameIndex, Offset);
- }
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
}
+#endif
/// Remove any STXVP[X] instructions and split them out into a pair of
/// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
@@ -1290,8 +1299,19 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
Register SrcReg = MI.getOperand(0).getReg();
bool IsLittleEndian = Subtarget.isLittleEndian();
bool IsKilled = MI.getOperand(0).isKill();
- spillRegPairs(MBB, II, DL, TII, SrcReg, FrameIndex, IsLittleEndian, IsKilled,
- /* TwoPairs */ false);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? 16 : 0);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? 0 : 16);
+
// Discard the original instruction.
MBB.erase(II);
}
@@ -1321,8 +1341,8 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- Register SrcReg = MI.getOperand(0).getReg();
bool IsKilled = MI.getOperand(0).isKill();
+ Register SrcReg = MI.getOperand(0).getReg();
bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
Register Reg =
@@ -1337,10 +1357,35 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
// adjust the offset of the store that is within the 64-byte stack slot.
if (IsPrimed)
BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
- if (DisableAutoPairedVecSt)
- spillRegPairs(MBB, II, DL, TII, Reg, FrameIndex, IsLittleEndian, IsKilled,
- /* TwoPairs */ true);
- else {
+ if (DisableAutoPairedVecSt) {
+ unsigned Offset = IsLittleEndian ? 48 : 0;
+ Register RegP0 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0);
+ Register RegP1 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ } else {
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
.addReg(Reg, getKillRegState(IsKilled)),
FrameIndex, IsLittleEndian ? 32 : 0);
>From 0bb2a26e11175786cbdc04cd3ab49d613603d5f7 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 30 May 2025 12:28:17 -0500
Subject: [PATCH 2/4] Simpliy handling for spilling acc reg with stx
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 106 +++++---------------
1 file changed, 27 insertions(+), 79 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 336f84c9002f0..a3a8eea33aef5 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1238,51 +1238,6 @@ static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
#endif
}
-#if 0
-static void spillRegPairs(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator II, DebugLoc DL,
- const TargetInstrInfo &TII, Register SrcReg,
- unsigned FrameIndex, bool IsLittleEndian) {
- MachineInstr &MI = *II;
- bool IsKilled = MI.getOperand(0).isKill();
- unsigned Offset = IsLittleEndian ? 48 : 0;
-
- // The register arithmetic in this function does not support virtual
- // registers.
- /*
- assert(!SrcReg.isVirtual() &&
- "Spilling register pairs does not support virtual registers.");
- */
-
- Register RegP0 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0);
- Register RegP1 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1);
-
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
-}
-#endif
-
/// Remove any STXVP[X] instructions and split them out into a pair of
/// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
/// the command line.
@@ -1300,12 +1255,14 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
bool IsLittleEndian = Subtarget.isLittleEndian();
bool IsKilled = MI.getOperand(0).isKill();
+ assert(PPC::VSRpRCRegClass.contains(SrcReg) &&
+ "Expecting STXVP to be utilizing a VSRp register.");
+
addFrameReference(
BuildMI(MBB, II, DL, TII.get(PPC::STXV))
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx0),
getKillRegState(IsKilled)),
FrameIndex, IsLittleEndian ? 16 : 0);
-
addFrameReference(
BuildMI(MBB, II, DL, TII.get(PPC::STXV))
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx1),
@@ -1341,12 +1298,10 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- bool IsKilled = MI.getOperand(0).isKill();
Register SrcReg = MI.getOperand(0).getReg();
+ bool IsKilled = MI.getOperand(0).isKill();
bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
- Register Reg =
- PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
bool IsLittleEndian = Subtarget.isLittleEndian();
emitAccSpillRestoreInfo(MBB, IsPrimed, false);
@@ -1358,40 +1313,33 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
if (IsPrimed)
BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
if (DisableAutoPairedVecSt) {
- unsigned Offset = IsLittleEndian ? 48 : 0;
- Register RegP0 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0);
- Register RegP1 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1);
-
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
+ auto spillPair = [&](Register Reg, int Offset) {
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? Offset - 16 : Offset + 16);
+ };
+ spillPair(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0),
+ IsLittleEndian ? 48 : 0);
+ spillPair(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
+ IsLittleEndian ? 16 : 32);
+ } else {
addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx0),
+ BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
+ .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0),
getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
+ FrameIndex, IsLittleEndian ? 32 : 0);
addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx1),
+ BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
+ .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
getKillRegState(IsKilled)),
- FrameIndex, Offset);
- } else {
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
- .addReg(Reg, getKillRegState(IsKilled)),
- FrameIndex, IsLittleEndian ? 32 : 0);
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
- .addReg(Reg + 1, getKillRegState(IsKilled)),
- FrameIndex, IsLittleEndian ? 0 : 32);
+ FrameIndex, IsLittleEndian ? 0 : 32);
}
if (IsPrimed && !IsKilled)
BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
>From 49b2ebf0384ea95bb73de23d2d0b0088ffd22cf5 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 5 Jun 2025 14:25:08 +0000
Subject: [PATCH 3/4] change to private function since it'll be needed for wacc
reg spilling when stxvp is disabled
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 63 +++++++++++----------
llvm/lib/Target/PowerPC/PPCRegisterInfo.h | 5 ++
2 files changed, 38 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index a3a8eea33aef5..03dd5e8b24e4b 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1238,6 +1238,30 @@ static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
#endif
}
+void PPCRegisterInfo::spillRegPair(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator II, DebugLoc DL,
+ const TargetInstrInfo &TII,
+ unsigned FrameIndex, bool IsLittleEndian,
+ bool IsKilled, Register Reg,
+ int Offset) const {
+
+ // This function does not support virtual registers.
+ assert(!Reg.isVirtual() &&
+ "Spilling register pairs does not support virtual registers.");
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? Offset - 16 : Offset + 16);
+}
+
/// Remove any STXVP[X] instructions and split them out into a pair of
/// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
/// the command line.
@@ -1252,22 +1276,11 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
Register SrcReg = MI.getOperand(0).getReg();
- bool IsLittleEndian = Subtarget.isLittleEndian();
bool IsKilled = MI.getOperand(0).isKill();
+ bool IsLittleEndian = Subtarget.isLittleEndian();
- assert(PPC::VSRpRCRegClass.contains(SrcReg) &&
- "Expecting STXVP to be utilizing a VSRp register.");
-
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, IsLittleEndian ? 16 : 0);
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, IsLittleEndian ? 0 : 16);
+ spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled, SrcReg,
+ IsLittleEndian ? 16 : 0);
// Discard the original instruction.
MBB.erase(II);
@@ -1313,22 +1326,12 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
if (IsPrimed)
BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
if (DisableAutoPairedVecSt) {
- auto spillPair = [&](Register Reg, int Offset) {
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, IsLittleEndian ? Offset - 16 : Offset + 16);
- };
- spillPair(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0),
- IsLittleEndian ? 48 : 0);
- spillPair(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
- IsLittleEndian ? 16 : 32);
+ spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled,
+ TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0),
+ IsLittleEndian ? 48 : 0);
+ spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled,
+ TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
+ IsLittleEndian ? 16 : 32);
} else {
addFrameReference(
BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 4b66ece534112..849f856b5419e 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -58,6 +58,11 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
DenseMap<unsigned, unsigned> ImmToIdxMap;
const PPCTargetMachine &TM;
+ void spillRegPair(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
+ DebugLoc DL, const TargetInstrInfo &TII,
+ unsigned FrameIndex, bool IsLittleEndian, bool IsKilled,
+ Register Reg, int Offset) const;
+
public:
PPCRegisterInfo(const PPCTargetMachine &TM);
>From 407bc353d542ba1e325e6c8f4e5c1b034b7f223d Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 5 Jun 2025 15:19:46 +0000
Subject: [PATCH 4/4] remove unintentional code move
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 03dd5e8b24e4b..ea34c1aba82e3 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1276,8 +1276,8 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
Register SrcReg = MI.getOperand(0).getReg();
- bool IsKilled = MI.getOperand(0).isKill();
bool IsLittleEndian = Subtarget.isLittleEndian();
+ bool IsKilled = MI.getOperand(0).isKill();
spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled, SrcReg,
IsLittleEndian ? 16 : 0);
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