[llvm] [AArch64] Extend usage of `XAR` instruction for fixed-length operations (PR #139460)

[David Green via llvm-commits]

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@@ -4606,7 +4606,36 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
     return false;
   }
 
-  if (!Subtarget->hasSHA3())
+  // We have Neon SHA3 XAR operation for v2i64 but for types
+  // v4i32, v8i16, v16i8 we can use SVE operations when SVE2-SHA3
+  // is available.
+  EVT SVT;
+  switch (VT.getSimpleVT().SimpleTy) {
+  case MVT::v4i32:
+    SVT = MVT::nxv4i32;
+    break;
+  case MVT::v8i16:
+    SVT = MVT::nxv8i16;
+    break;
+  case MVT::v16i8:
+    SVT = MVT::nxv16i8;
+    break;
+  case MVT::v1i64:
+  case MVT::v2i32:
+  case MVT::v4i16:
+  case MVT::v8i8:
----------------
davemgreen wrote:

I think they need to have the same element size, for the rotate. It looks like it should be OK to treat the 64bit vectors as the bottom lanes of either a 128bit or scalable vector, so long as they have the correct inserts/extracts.

https://github.com/llvm/llvm-project/pull/139460