[llvm] [AArch64] Extend usage of `XAR` instruction for fixed-length operations (PR #139460)

[David Green via llvm-commits]

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@@ -4632,41 +4661,68 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
   SDValue Imm = CurDAG->getTargetConstant(
       ShAmt, DL, N0.getOperand(1).getValueType(), false);
 
-  if (ShAmt + HsAmt != 64)
+  unsigned VTSizeInBits = VT.getScalarSizeInBits();
+  if (ShAmt + HsAmt != VTSizeInBits)
     return false;
 
   if (!IsXOROperand) {
     SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i64);
-    SDNode *MOV =
-        CurDAG->getMachineNode(AArch64::MOVIv2d_ns, DL, MVT::v2i64, Zero);
+    SDNode *MOV = CurDAG->getMachineNode(AArch64::MOVIv2d_ns, DL, SVT, Zero);
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davemgreen wrote:

I think the SVT here might need to be a 128bit vector so that the types are correct, as MOVIv2d_ns will always produce a 128bit vector. Maybe using `VT.is64BitVector() ? VT.getDoubleNumVectorElementsVT() : VT;`?

https://github.com/llvm/llvm-project/pull/139460