[llvm] [CGP] Bail out if (Base|Scaled)Reg does not dominate insert point. (PR #142949)

[Florian Hahn via llvm-commits]

https://github.com/fhahn created https://github.com/llvm/llvm-project/pull/142949

(Base|Scaled)Reg may not dominate the chosen insert point, if there are multiple uses of the address. Bail out if that's the case, otherwise we will generate invalid IR.

In some cases, we could probably adjust the insert point or hoist the (Base|Scaled)Reg.

Fixes https://github.com/llvm/llvm-project/issues/142830

>From d9b678e4125a9461d4dad5b5cec30c82f2bdf919 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Thu, 5 Jun 2025 12:36:01 +0100
Subject: [PATCH] [CGP] Bail out if (Base|Scaled)Reg does not dominate insert
 point.

(Base|Scaled)Reg may not dominate the chosen insert point, if there are
multiple uses of the address. Bail out if that's the case, otherwise we
will generate invalid IR.

In some cases, we could probably adjust the insert point or hoist the
(Base|Scaled)Reg.
---
 llvm/lib/CodeGen/CodeGenPrepare.cpp           | 11 ++++-
 .../X86/sink-addrmode-reg-does-not-geps.ll    | 48 +++++++++++++++++++
 2 files changed, 57 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-reg-does-not-geps.ll

diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 822ed6283117c..222f0f37fed50 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -5945,8 +5945,15 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
   // The current BB may be optimized multiple times, we can't guarantee the
   // reuse of Addr happens later, call findInsertPos to find an appropriate
   // insert position.
-  IRBuilder<> Builder(MemoryInst->getParent(),
-                      findInsertPos(Addr, MemoryInst, SunkAddr));
+  auto InsertPos = findInsertPos(Addr, MemoryInst, SunkAddr);
+
+  // TODO: Adjust insert point considering (Base|Scaled)Reg if possible.
+  if (!SunkAddr &&
+      ((AddrMode.BaseReg && !DT->dominates(AddrMode.BaseReg, &*InsertPos)) ||
+       (AddrMode.ScaledReg && !DT->dominates(AddrMode.ScaledReg, &*InsertPos))))
+    return Modified;
+
+  IRBuilder<> Builder(MemoryInst->getParent(), InsertPos);
 
   if (SunkAddr) {
     LLVM_DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-reg-does-not-geps.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-reg-does-not-geps.ll
new file mode 100644
index 0000000000000..38598205c54f9
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-reg-does-not-geps.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' %s | FileCheck %s
+
+
+target triple = "x86_64-unknown-linux"
+
+declare i1 @cond(float)
+
+define void @test(ptr %src) {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:  [[BB:.*]]:
+; CHECK-NEXT:    br label %[[LOOP:.*]]
+; CHECK:       [[LOOP]]:
+; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[BB]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT:    [[SUNKADDR2:%.*]] = mul i64 [[IV_NEXT]], 2
+; CHECK-NEXT:    [[SUNKADDR3:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[SUNKADDR2]]
+; CHECK-NEXT:    [[SUNKADDR4:%.*]] = getelementptr i8, ptr [[SUNKADDR3]], i64 6
+; CHECK-NEXT:    [[L_0:%.*]] = load float, ptr [[SUNKADDR4]], align 4
+; CHECK-NEXT:    [[SUNKADDR:%.*]] = mul i64 [[IV]], 2
+; CHECK-NEXT:    [[SUNKADDR1:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[SUNKADDR]]
+; CHECK-NEXT:    [[L_1:%.*]] = load float, ptr [[SUNKADDR1]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = call i1 @cond(float [[L_0]])
+; CHECK-NEXT:    [[C:%.*]] = call i1 @cond(float [[L_1]])
+; CHECK-NEXT:    br i1 [[C]], label %[[LOOP]], label %[[EXIT:.*]]
+; CHECK:       [[EXIT]]:
+; CHECK-NEXT:    ret void
+;
+bb:
+  %gep.base = getelementptr i8, ptr %src, i64 8
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %bb ], [ %iv.next, %loop ]
+  %iv.shl = shl i64 %iv, 1
+  %gep.shl = getelementptr i8, ptr %gep.base, i64 %iv.shl
+  %gep.sub = getelementptr i8, ptr %gep.shl, i64 -8
+  %iv.next = add i64 %iv, 1
+  %l.0 = load float, ptr %gep.shl, align 4
+  %l.1 = load float, ptr %gep.sub, align 4
+  call i1 @cond(float %l.0)
+  %c = call i1 @cond(float %l.1)
+  br i1 %c, label %loop, label %exit
+
+exit:
+  ret void
+}