[llvm] [RISCV] Select unsigned bitfield insert for XAndesPerf (PR #142737)

[Jim Lin via llvm-commits]

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@@ -1348,13 +1348,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
           // e.g.
           //     (and (shl x, 12), 0x00fff000)
           //     If XLen = 32 and C2 = 12, then
-          //       Len = 32 - 8 - 12 = 12,
-          //       Lsb = 32 - 8 - 1 = 23 and Msb = 12
-          //     -> nds.bfoz x, 12, 23
-          const unsigned Len = XLen - Leading - C2;
-          const unsigned Lsb = XLen - Leading - 1;
-          // If Len is 1, the Msb will be 0 instead of C2.
-          unsigned Msb = Len == 1 ? 0 : C2;
+          //     Msb = 32 - 8 - 1 = 23 and Lsb = 12
+          const unsigned Msb = XLen - Leading - 1;
+          // If Msb is equal to C2, the Lsb will be 0 instead of C2.
+          unsigned Lsb = Msb == C2 ? 0 : C2;
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tclin914 wrote:

Done. Thanks.

https://github.com/llvm/llvm-project/pull/142737