[llvm] eca616f - [RISCV] Fix schedule info for Zqvdotq (#142717)

[via llvm-commits]

Author: Jim Lin
Date: 2025-06-05T12:22:43+08:00
New Revision: eca616f376eccfeaccb01fcfc6c833e571b7f1e1

URL: https://github.com/llvm/llvm-project/commit/eca616f376eccfeaccb01fcfc6c833e571b7f1e1
DIFF: https://github.com/llvm/llvm-project/commit/eca616f376eccfeaccb01fcfc6c833e571b7f1e1.diff

LOG: [RISCV] Fix schedule info for Zqvdotq (#142717)

The instructions in Zqvdotq is dot-product operation. So the schedule
info should be VIMulAdd rather than VIALU.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
index ea3c53cb0a5dd..27959eaccd904 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
@@ -37,11 +37,11 @@ let HasPassthruOp = true, HasMaskOp = true in {
 multiclass VPseudoVQDOT_VV_VX {
   foreach m = MxSet<32>.m in {
     defm "" : VPseudoBinaryV_VV<m>,
-            SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,
-                        forcePassthruRead=true>;
+              SchedBinary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV", m.MX,
+                          forcePassthruRead=true>;
     defm "" : VPseudoBinaryV_VX<m>,
-            SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX,
-                        forcePassthruRead=true>;
+              SchedBinary<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddX", m.MX,
+                          forcePassthruRead=true>;
   }
 }