[llvm] 19592fe - [AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)

[via llvm-commits]

Author: Kazu Hirata
Date: 2025-06-04T12:30:56-07:00
New Revision: 19592fe0a37374e1dd631b7699590500b5dec136

URL: https://github.com/llvm/llvm-project/commit/19592fe0a37374e1dd631b7699590500b5dec136
DIFF: https://github.com/llvm/llvm-project/commit/19592fe0a37374e1dd631b7699590500b5dec136.diff

LOG: [AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)

Note that def_instructions is defined as:

  inline iterator_range<def_instr_iterator>
  def_instructions(Register Reg) const {
    return make_range(def_instr_begin(Reg), def_instr_end());
  }

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
    llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
index 824bbcfb48cfe..7f75f2797124e 100644
--- a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
+++ b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
@@ -324,11 +324,8 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
       if (MI.getOpcode() != R600::REG_SEQUENCE) {
         if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
           Register Reg = MI.getOperand(1).getReg();
-          for (MachineRegisterInfo::def_instr_iterator
-               It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end();
-               It != E; ++It) {
-            RemoveMI(&(*It));
-          }
+          for (MachineInstr &DefMI : MRI->def_instructions(Reg))
+            RemoveMI(&DefMI);
         }
         continue;
       }

diff  --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
index 2bbbbf4db02db..fd28abeb887c2 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -287,13 +287,10 @@ void SIScheduleBlock::fastSchedule() {
 static bool isDefBetween(Register Reg, SlotIndex First, SlotIndex Last,
                          const MachineRegisterInfo *MRI,
                          const LiveIntervals *LIS) {
-  for (MachineRegisterInfo::def_instr_iterator
-       UI = MRI->def_instr_begin(Reg),
-       UE = MRI->def_instr_end(); UI != UE; ++UI) {
-    const MachineInstr* MI = &*UI;
-    if (MI->isDebugValue())
+  for (const MachineInstr &MI : MRI->def_instructions(Reg)) {
+    if (MI.isDebugValue())
       continue;
-    SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
+    SlotIndex InstSlot = LIS->getInstructionIndex(MI).getRegSlot();
     if (InstSlot >= First && InstSlot <= Last)
       return true;
   }

diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 511ea4125c8ec..b76823a128e07 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -4060,9 +4060,9 @@ SIRegisterInfo::getNumDefinedPhysRegs(const MachineRegisterInfo &MRI,
                                       const TargetRegisterClass &RC) const {
   for (MCPhysReg Reg : reverse(RC.getRegisters())) {
     for (MCRegAliasIterator AI(Reg, this, true); AI.isValid(); ++AI) {
-      if (std::any_of(
-              MRI.def_instr_begin(*AI), MRI.def_instr_end(),
-              [](const MachineInstr &MI) { return !MI.isImplicitDef(); }))
+      if (llvm::any_of(MRI.def_instructions(*AI), [](const MachineInstr &MI) {
+            return !MI.isImplicitDef();
+          }))
         return getHWRegIndex(Reg) + 1;
     }
   }