[llvm] [RISCV] Guard the alternative static chain register use on ILP32E/LP64E (PR #142715)

[Craig Topper via llvm-commits]

================
@@ -338,6 +338,10 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
   bool HasCFBranch =
       Subtarget.hasStdExtZicfilp() &&
       MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
+  if (HasCFBranch && (Subtarget.isRV32() && Subtarget.hasStdExtE()))
----------------
topperc wrote:

> Yes, and this should be checking for the E ABIs, not the E Architectures.

That's not what the rest of the compiler does.

```
  // There are only 16 GPRs for RVE.                                             
  if (Subtarget.hasStdExtE())                                                    
    for (MCPhysReg Reg = RISCV::X16_H; Reg <= RISCV::X31_H; Reg++)               
      markSuperRegs(Reserved, Reg);      
```

https://github.com/llvm/llvm-project/pull/142715