[llvm] [NFC][AMDGPU] Add lit tests for FMA combining with freeze and nnan variants (PR #142628)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 4 08:27:47 PDT 2025
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/142628
>From 09045833b79ba8c53000a56e8436a5daee8a82a3 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 3 Jun 2025 15:02:36 +0000
Subject: [PATCH 1/3] [DAG][AMDGPU] Add lit tests for FMA combining with freeze
and nnan variants
---
.../CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll | 106 ++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
diff --git a/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll b/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
new file mode 100644
index 0000000000000..dbf5636ae03ed
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
@@ -0,0 +1,106 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s
+
+define float @fma_from_freeze_mul_add_left(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_add_left:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %add = fadd reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
+ ret float %add
+}
+
+define float @fma_from_freeze_mul_add_left_with_nnan(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_add_left_with_nnan:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_add_f32_e32 v0, 1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %add = fadd reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
+ ret float %add
+}
+
+define float @fma_from_freeze_mul_add_right(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_add_right:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %add = fadd reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
+ ret float %add
+}
+
+define float @fma_from_freeze_mul_add_right_with_nnan(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_add_right_with_nnan:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_add_f32_e32 v0, 1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %add = fadd reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
+ ret float %add
+}
+
+define float @fma_from_freeze_mul_sub_left(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_sub_left:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_fma_f32 v0, v0, v1, -1.0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %sub = fsub reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
+ ret float %sub
+}
+
+define float @fma_from_freeze_mul_sub_left_with_nnan(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_sub_left_with_nnan:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_add_f32_e32 v0, -1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %sub = fsub reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
+ ret float %sub
+}
+
+define float @fma_from_freeze_mul_sub_right(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_sub_right:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_fma_f32 v0, -v0, v1, 1.0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %sub = fsub reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
+ ret float %sub
+}
+
+define float @fma_from_freeze_mul_sub_right_with_nnan(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_sub_right_with_nnan:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_sub_f32_e32 v0, 1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %sub = fsub reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
+ ret float %sub
+}
>From 13d38212a054c7cf2a57f8a69a29860103b3890d Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 3 Jun 2025 15:18:53 +0000
Subject: [PATCH 2/3] [AMDGPU] Update.
---
llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll b/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
index dbf5636ae03ed..adcd989d6d02a 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s
define float @fma_from_freeze_mul_add_left(float %x, float %y) {
; CHECK-LABEL: fma_from_freeze_mul_add_left:
>From 9e6d5f843187d272675190f70375c046c8d228bc Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Wed, 4 Jun 2025 20:21:34 +0800
Subject: [PATCH 3/3] [AMDGPU] Update lit test.
---
.../CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll | 32 +++++++++----------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll b/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
index adcd989d6d02a..a1b2dbda687fb 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
@@ -7,9 +7,9 @@ define float @fma_from_freeze_mul_add_left(float %x, float %y) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
; CHECK-NEXT: s_setpc_b64 s[30:31]
- %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul = fmul contract float %x, %y
%mul.fr = freeze float %mul
- %add = fadd reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
+ %add = fadd contract float %mul.fr, 1.000000e+00
ret float %add
}
@@ -21,9 +21,9 @@ define float @fma_from_freeze_mul_add_left_with_nnan(float %x, float %y) {
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-NEXT: v_add_f32_e32 v0, 1.0, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
- %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul = fmul nnan contract afn float %x, %y
%mul.fr = freeze float %mul
- %add = fadd reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
+ %add = fadd nnan contract float %mul.fr, 1.000000e+00
ret float %add
}
@@ -33,9 +33,9 @@ define float @fma_from_freeze_mul_add_right(float %x, float %y) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
; CHECK-NEXT: s_setpc_b64 s[30:31]
- %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul = fmul contract float %x, %y
%mul.fr = freeze float %mul
- %add = fadd reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
+ %add = fadd contract float 1.000000e+00, %mul.fr
ret float %add
}
@@ -47,9 +47,9 @@ define float @fma_from_freeze_mul_add_right_with_nnan(float %x, float %y) {
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-NEXT: v_add_f32_e32 v0, 1.0, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
- %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul = fmul nnan contract float %x, %y
%mul.fr = freeze float %mul
- %add = fadd reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
+ %add = fadd nnan contract float 1.000000e+00, %mul.fr
ret float %add
}
@@ -59,9 +59,9 @@ define float @fma_from_freeze_mul_sub_left(float %x, float %y) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_fma_f32 v0, v0, v1, -1.0
; CHECK-NEXT: s_setpc_b64 s[30:31]
- %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul = fmul contract float %x, %y
%mul.fr = freeze float %mul
- %sub = fsub reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
+ %sub = fsub contract float %mul.fr, 1.000000e+00
ret float %sub
}
@@ -73,9 +73,9 @@ define float @fma_from_freeze_mul_sub_left_with_nnan(float %x, float %y) {
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-NEXT: v_add_f32_e32 v0, -1.0, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
- %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul = fmul nnan contract float %x, %y
%mul.fr = freeze float %mul
- %sub = fsub reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
+ %sub = fsub nnan contract float %mul.fr, 1.000000e+00
ret float %sub
}
@@ -85,9 +85,9 @@ define float @fma_from_freeze_mul_sub_right(float %x, float %y) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_fma_f32 v0, -v0, v1, 1.0
; CHECK-NEXT: s_setpc_b64 s[30:31]
- %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul = fmul contract float %x, %y
%mul.fr = freeze float %mul
- %sub = fsub reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
+ %sub = fsub contract float 1.000000e+00, %mul.fr
ret float %sub
}
@@ -99,8 +99,8 @@ define float @fma_from_freeze_mul_sub_right_with_nnan(float %x, float %y) {
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-NEXT: v_sub_f32_e32 v0, 1.0, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
- %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul = fmul nnan contract float %x, %y
%mul.fr = freeze float %mul
- %sub = fsub reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
+ %sub = fsub nnan contract float 1.000000e+00, %mul.fr
ret float %sub
}
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