[llvm] [AArch64] Spare N2I roundtrip when splatting float comparison (PR #141806)

[David Green via llvm-commits]

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@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define <8 x half> @dup_v8i16(half %a, half %b) {
+  ; CHECK-LABEL: dup_v8i16:
+  ; CHECK:       // %bb.0: // %entry
+  ; CHECK-NEXT:    fcvt s1, h1
+  ; CHECK-NEXT:    fcvt s0, h0
+  ; CHECK-NEXT:    fcmeq s0, s0, s1
+  ; CHECK-NEXT:    ret
+  entry:
+  %0 = fcmp oeq half %a, %b
+  %vcmpd.i = sext i1 %0 to i16
+  %vecinit.i = insertelement <8 x i16> poison, i16 %vcmpd.i, i64 0
+  %1 = bitcast <8 x i16> %vecinit.i to <8 x half>
+  ret <8 x half> %1
+}
+
+define <1 x float> @dup_v1i32(float %a, float %b) {
----------------
davemgreen wrote:

Can you add this test case, and make sure there is at least one with a zext instead of a sext
```
define i32 @dup_v1i32_sonly(float %a, float %b) {
; CHECK-LABEL: dup_v1i32_sonly:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcmeq s0, s0, s1
; CHECK-NEXT:    fmov w0, s0
; CHECK-NEXT:    ret
entry:
  %0 = fcmp oeq float %a, %b
  %vcmpd.i = sext i1 %0 to i32
  ret i32 %vcmpd.i
}
```

https://github.com/llvm/llvm-project/pull/141806