[llvm] [RISCV] Guard the alternative static chain register use on RV32E (PR #142715)

[Kito Cheng via llvm-commits]

================
@@ -333,19 +333,22 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
   unsigned XLen = Subtarget.getXLen();
   MVT XLenVT = Subtarget.getXLenVT();
 
-  // Static chain parameter must not be passed in normal argument registers,
-  // so we assign t2/t3 for it as done in GCC's __builtin_call_with_static_chain
-  bool HasCFBranch =
-      Subtarget.hasStdExtZicfilp() &&
-      MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
-  if (HasCFBranch && (Subtarget.isRV32() && Subtarget.hasStdExtE()))
-    reportFatalUsageError(
-        "Alternative static chain register is not supported on RV32E");
-
-  // Normal: t2, Branch control flow protection: t3
-  const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;
-
   if (ArgFlags.isNest()) {
+    // Static chain parameter must not be passed in normal argument registers,
+    // so we assign t2/t3 for it as done in GCC's
+    // __builtin_call_with_static_chain
+    bool HasCFBranch =
+        Subtarget.hasStdExtZicfilp() &&
+        MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
+
+    // Normal: t2, Branch control flow protection: t3
+    const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;
+
+    RISCVABI::ABI ABI = Subtarget.getTargetABI();
+    if (HasCFBranch &&
+        (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E))
+      reportFatalUsageError(
+          "Alternative static chain register t3 is not usable with EABI.");
----------------
kito-cheng wrote:

EABI might be confusing because it's defined in other target like ARM32
```suggestion
          "Alternative static chain register t3 is not usable with ILP32E or LP64E ABI.");
```

https://github.com/llvm/llvm-project/pull/142715