[llvm] 3894bdc - [AArch64][GlobalISel] Add regbank handling for scalar rda intrinsics.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 3 23:06:20 PDT 2025
Author: David Green
Date: 2025-06-04T07:06:15+01:00
New Revision: 3894bdc3c94eae51e7587cb03f456a71fd03d0e1
URL: https://github.com/llvm/llvm-project/commit/3894bdc3c94eae51e7587cb03f456a71fd03d0e1
DIFF: https://github.com/llvm/llvm-project/commit/3894bdc3c94eae51e7587cb03f456a71fd03d0e1.diff
LOG: [AArch64][GlobalISel] Add regbank handling for scalar rda intrinsics.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 6bd3fd182485d..80e098eb1ea15 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -476,6 +476,11 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
case Intrinsic::aarch64_neon_facgt:
case Intrinsic::aarch64_neon_fabd:
case Intrinsic::aarch64_sisd_fabd:
+ case Intrinsic::aarch64_neon_sqrdmlah:
+ case Intrinsic::aarch64_neon_sqrdmlsh:
+ case Intrinsic::aarch64_neon_sqrdmulh:
+ case Intrinsic::aarch64_neon_sqadd:
+ case Intrinsic::aarch64_neon_sqsub:
return true;
case Intrinsic::aarch64_neon_saddlv: {
const LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll b/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
index 32f5798040f20..bbea8f7b93f02 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
@@ -1,22 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+rdm | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+rdm -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-; CHECK-GI: warning: Instruction selection used fallback path for test_sqrdmlah_extracted_lane_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrdmlahq_extracted_lane_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrdmlsh_extracted_lane_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrdmlshq_extracted_lane_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrdmlah_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrdmlsh_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrdmlah_extract_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrdmlsh_extract_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vqrdmlahs_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vqrdmlahs_lane_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vqrdmlahs_laneq_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vqrdmlshs_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vqrdmlshs_lane_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vqrdmlshs_laneq_s32
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+rdm -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
@@ -719,14 +704,24 @@ entry:
}
define i32 @test_vqrdmlahs_lane_s32(i32 %a, i32 %b, <2 x i32> %c) {
-; CHECK-LABEL: test_vqrdmlahs_lane_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov s1, w0
-; CHECK-NEXT: fmov s2, w1
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqrdmlah s1, s2, v0.s[1]
-; CHECK-NEXT: fmov w0, s1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqrdmlahs_lane_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov s1, w0
+; CHECK-SD-NEXT: fmov s2, w1
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqrdmlah s1, s2, v0.s[1]
+; CHECK-SD-NEXT: fmov w0, s1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqrdmlahs_lane_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: fmov s1, w0
+; CHECK-GI-NEXT: fmov s2, w1
+; CHECK-GI-NEXT: mov s0, v0.s[1]
+; CHECK-GI-NEXT: sqrdmlah s1, s2, s0
+; CHECK-GI-NEXT: fmov w0, s1
+; CHECK-GI-NEXT: ret
entry:
%vget_lane = extractelement <2 x i32> %c, i64 1
%vqrdmlahs_s32.i = tail call i32 @llvm.aarch64.neon.sqrdmlah.i32(i32 %a, i32 %b, i32 %vget_lane) #4
@@ -889,14 +884,24 @@ entry:
}
define i32 @test_vqrdmlshs_lane_s32(i32 %a, i32 %b, <2 x i32> %c) {
-; CHECK-LABEL: test_vqrdmlshs_lane_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov s1, w0
-; CHECK-NEXT: fmov s2, w1
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqrdmlsh s1, s2, v0.s[1]
-; CHECK-NEXT: fmov w0, s1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_vqrdmlshs_lane_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov s1, w0
+; CHECK-SD-NEXT: fmov s2, w1
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqrdmlsh s1, s2, v0.s[1]
+; CHECK-SD-NEXT: fmov w0, s1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vqrdmlshs_lane_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: fmov s1, w0
+; CHECK-GI-NEXT: fmov s2, w1
+; CHECK-GI-NEXT: mov s0, v0.s[1]
+; CHECK-GI-NEXT: sqrdmlsh s1, s2, s0
+; CHECK-GI-NEXT: fmov w0, s1
+; CHECK-GI-NEXT: ret
entry:
%vget_lane = extractelement <2 x i32> %c, i64 1
%vqrdmlshs_s32.i = tail call i32 @llvm.aarch64.neon.sqrdmlsh.i32(i32 %a, i32 %b, i32 %vget_lane) #4
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