[llvm] [RISCV] Implement base scheduling model for andes 45 series processor. (PR #141008)

[Jim Lin via llvm-commits]

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@@ -0,0 +1,126 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -timeline -iterations=1 < %s | FileCheck %s
+
+# Two ALUs without dependency can be dispatched in the same cycle.
+add a0, a0, a0
+sub a1, a1, a1
+
+# Otherwise, they can't be dispatched in the same cycle.
+addw a0, a0, a0
+subw a0, a0, a0
+
+// MDU
+mul a0, a0, a0
+div a0, a0, a0
+
+// Memory
+lb a0, 4(a1)
+lw a0, 4(a1)
+sb a0, 4(a1)
+sw a0, 4(a1)
+
+// CSR
+csrrw a0, mstatus, zero
+
+// Bitmanip
+sh1add a0, a0, a0
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tclin914 wrote:

> Add more test coverage?

Done. Thanks.

https://github.com/llvm/llvm-project/pull/141008