[llvm] [RISCV] Fix coalescing vsetvlis when AVL and vl registers are the same (PR #141941)

[Min-Yih Hsu via llvm-commits]

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@@ -1698,13 +1698,24 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
           MI.getOperand(0).setReg(DefReg);
           MI.getOperand(0).setIsDead(false);
 
+          // Move the AVL from MI to NextMI
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mshockwave wrote:

should this be "moving from NextMI to MI"?

https://github.com/llvm/llvm-project/pull/141941