[llvm] [NFCI][PromoteMem2Reg] Don't handle the first successor out of order (PR #142464)
Vitaly Buka via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 3 10:20:22 PDT 2025
https://github.com/vitalybuka updated https://github.com/llvm/llvm-project/pull/142464
>From a56a52922e9c7663071b55f4288093c13cb6b191 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at google.com>
Date: Mon, 2 Jun 2025 12:39:01 -0700
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
=?UTF-8?q?anges=20to=20main=20this=20commit=20is=20based=20on?=
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Created using spr 1.3.6
[skip ci]
---
.../Utils/PromoteMemoryToRegister.cpp | 22 +++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
index 6ba64968193cf..d84b07bd1457c 100644
--- a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
+++ b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
@@ -424,8 +424,8 @@ struct PromoteMem2Reg {
const SmallPtrSetImpl<BasicBlock *> &DefBlocks,
SmallPtrSetImpl<BasicBlock *> &LiveInBlocks);
void RenamePass(BasicBlock *BB, BasicBlock *Pred,
- RenamePassData::ValVector &IncVals,
- RenamePassData::LocationVector &IncLocs,
+ RenamePassData::ValVector IncVals,
+ RenamePassData::LocationVector IncLocs,
std::vector<RenamePassData> &Worklist);
bool QueuePhiNode(BasicBlock *BB, unsigned AllocaIdx, unsigned &Version);
@@ -869,7 +869,8 @@ void PromoteMem2Reg::run() {
RenamePassData RPD = std::move(RenamePassWorkList.back());
RenamePassWorkList.pop_back();
// RenamePass may add new worklist entries.
- RenamePass(RPD.BB, RPD.Pred, RPD.Values, RPD.Locations, RenamePassWorkList);
+ RenamePass(RPD.BB, RPD.Pred, std::move(RPD.Values),
+ std::move(RPD.Locations), RenamePassWorkList);
} while (!RenamePassWorkList.empty());
// Remove the allocas themselves from the function.
@@ -1096,10 +1097,9 @@ static void updateForIncomingValueLocation(PHINode *PN, DebugLoc DL,
/// IncomingVals indicates what value each Alloca contains on exit from the
/// predecessor block Pred.
void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
- RenamePassData::ValVector &IncomingVals,
- RenamePassData::LocationVector &IncomingLocs,
+ RenamePassData::ValVector IncomingVals,
+ RenamePassData::LocationVector IncomingLocs,
std::vector<RenamePassData> &Worklist) {
-NextIteration:
// If we are inserting any phi nodes into this BB, they will already be in the
// block.
if (PHINode *APN = dyn_cast<PHINode>(BB->begin())) {
@@ -1222,17 +1222,17 @@ void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
// Keep track of the successors so we don't visit the same successor twice
SmallPtrSet<BasicBlock *, 8> VisitedSuccs;
- // Handle the first successor without using the worklist.
+ // Handle the first successor after the rest, to mimic legacy behaviour.
+ // FIXME: Handle them in regular order.
VisitedSuccs.insert(*I);
- Pred = BB;
- BB = *I;
++I;
for (; I != E; ++I)
if (VisitedSuccs.insert(*I).second)
- Worklist.emplace_back(*I, Pred, IncomingVals, IncomingLocs);
+ Worklist.emplace_back(*I, BB, IncomingVals, IncomingLocs);
- goto NextIteration;
+ Worklist.emplace_back(*succ_begin(BB), BB, std::move(IncomingVals),
+ std::move(IncomingLocs));
}
void llvm::PromoteMemToReg(ArrayRef<AllocaInst *> Allocas, DominatorTree &DT,
>From e210bc9c231ab211c594ce48bce4331f7fad57f8 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at google.com>
Date: Mon, 2 Jun 2025 12:43:05 -0700
Subject: [PATCH 2/3] test
Created using spr 1.3.6
---
.../Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll b/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
index 349a18148460f..a29c6a2fdd642 100644
--- a/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
+++ b/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
@@ -43,7 +43,7 @@ define i32 @foo(i32 %x) #0 section ".tcm_text" {
; DISABLE: sw.default:
; DISABLE-NEXT: br label [[RETURN]]
; DISABLE: return:
-; DISABLE-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 19, [[SW_DEFAULT]] ], [ 33, [[SW_BB5]] ], [ 12, [[SW_BB4]] ], [ 22, [[SW_BB3]] ], [ 14, [[SW_BB2]] ], [ 20, [[SW_BB1]] ], [ 9, [[ENTRY:%.*]] ]
+; DISABLE-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 19, [[SW_DEFAULT]] ], [ 20, [[SW_BB1]] ], [ 14, [[SW_BB2]] ], [ 22, [[SW_BB3]] ], [ 12, [[SW_BB4]] ], [ 33, [[SW_BB5]] ], [ 9, [[ENTRY:%.*]] ]
; DISABLE-NEXT: ret i32 [[RETVAL_0]]
;
entry:
>From 7fced809ccd3abd1d43e82e2734535a707ee35f8 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at google.com>
Date: Mon, 2 Jun 2025 13:34:33 -0700
Subject: [PATCH 3/3] rebase
Created using spr 1.3.6
---
.../Utils/PromoteMemoryToRegister.cpp | 55 ++++++++++++-------
1 file changed, 34 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
index d420aa7a931a0..7274d8ccd699b 100644
--- a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
+++ b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
@@ -392,6 +392,15 @@ struct PromoteMem2Reg {
/// number.
SmallVector<unsigned> BBNumPreds;
+ /// The state of incoming values for the current DFS step.
+ RenamePassData::ValVector IncomingVals;
+
+ /// The state of incoming locations for the current DFS step.
+ RenamePassData::LocationVector IncomingLocs;
+
+ // DFS work stack.
+ SmallVector<RenamePassData, 8> Worklist;
+
/// Whether the function has the no-signed-zeros-fp-math attribute set.
bool NoSignedZeros = false;
@@ -423,10 +432,7 @@ struct PromoteMem2Reg {
void ComputeLiveInBlocks(AllocaInst *AI, AllocaInfo &Info,
const SmallPtrSetImpl<BasicBlock *> &DefBlocks,
SmallPtrSetImpl<BasicBlock *> &LiveInBlocks);
- void RenamePass(BasicBlock *BB, BasicBlock *Pred,
- RenamePassData::ValVector IncVals,
- RenamePassData::LocationVector IncLocs,
- std::vector<RenamePassData> &Worklist);
+ void RenamePass(BasicBlock *BB, BasicBlock *Pred);
bool QueuePhiNode(BasicBlock *BB, unsigned AllocaIdx, unsigned &Version);
/// Delete dbg.assigns that have been demoted to dbg.values.
@@ -438,6 +444,20 @@ struct PromoteMem2Reg {
DVR->eraseFromParent();
DVRAssignsToDelete.clear();
}
+
+ void pushToWorklist(BasicBlock *BB, BasicBlock *Pred,
+ RenamePassData::ValVector IncVals,
+ RenamePassData::LocationVector IncLocs) {
+ Worklist.emplace_back(BB, Pred, std::move(IncVals), std::move(IncLocs));
+ }
+
+ RenamePassData popFromWorklist() {
+ RenamePassData R = std::move(Worklist.back());
+ Worklist.pop_back();
+ IncomingVals = std::move(R.Values);
+ IncomingLocs = std::move(R.Locations);
+ return R;
+ }
};
} // end anonymous namespace
@@ -849,29 +869,26 @@ void PromoteMem2Reg::run() {
// Set the incoming values for the basic block to be null values for all of
// the alloca's. We do this in case there is a load of a value that has not
// been stored yet. In this case, it will get this null value.
- RenamePassData::ValVector Values(Allocas.size());
+ IncomingVals.assign(Allocas.size(), nullptr);
for (unsigned i = 0, e = Allocas.size(); i != e; ++i)
- Values[i] = UndefValue::get(Allocas[i]->getAllocatedType());
+ IncomingVals[i] = UndefValue::get(Allocas[i]->getAllocatedType());
// When handling debug info, treat all incoming values as if they have unknown
// locations until proven otherwise.
- RenamePassData::LocationVector Locations(Allocas.size());
+ IncomingLocs.assign(Allocas.size(), {});
// The renamer uses the Visited set to avoid infinite loops.
Visited.resize(F.getMaxBlockNumber());
// Walks all basic blocks in the function performing the SSA rename algorithm
// and inserting the phi nodes we marked as necessary
- std::vector<RenamePassData> RenamePassWorkList;
- RenamePassWorkList.emplace_back(&F.front(), nullptr, std::move(Values),
- std::move(Locations));
+ pushToWorklist(&F.front(), nullptr, std::move(IncomingVals),
+ std::move(IncomingLocs));
do {
- RenamePassData RPD = std::move(RenamePassWorkList.back());
- RenamePassWorkList.pop_back();
+ RenamePassData RPD = popFromWorklist();
// RenamePass may add new worklist entries.
- RenamePass(RPD.BB, RPD.Pred, std::move(RPD.Values),
- std::move(RPD.Locations), RenamePassWorkList);
- } while (!RenamePassWorkList.empty());
+ RenamePass(RPD.BB, RPD.Pred);
+ } while (!Worklist.empty());
// Remove the allocas themselves from the function.
for (Instruction *A : Allocas) {
@@ -1096,10 +1113,7 @@ static void updateForIncomingValueLocation(PHINode *PN, DebugLoc DL,
///
/// IncomingVals indicates what value each Alloca contains on exit from the
/// predecessor block Pred.
-void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
- RenamePassData::ValVector IncomingVals,
- RenamePassData::LocationVector IncomingLocs,
- std::vector<RenamePassData> &Worklist) {
+void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred) {
// If we are inserting any phi nodes into this BB, they will already be in the
// block.
if (PHINode *APN = dyn_cast<PHINode>(BB->begin())) {
@@ -1226,8 +1240,7 @@ void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
IncomingVals = Worklist.back().Values;
IncomingLocs = Worklist.back().Locations;
}
- Worklist.emplace_back(S, BB, std::move(IncomingVals),
- std::move(IncomingLocs));
+ pushToWorklist(S, BB, std::move(IncomingVals), std::move(IncomingLocs));
}
}
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