[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Chris Jackson via llvm-commits]

================
@@ -2378,16 +2379,54 @@ def : AMDGPUPat <
 let True16Predicate = NotHasTrue16BitInsts in {
 def : ROTRPattern <V_ALIGNBIT_B32_e64>;
 
+def : AMDGPUPat <
+  (rotr v2i32:$src0, v2i32:$src1),
+  (REG_SEQUENCE VReg_64,
+    (V_ALIGNBIT_B32_e64
+      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
+      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
+      (i32 (EXTRACT_SUBREG VReg_64:$src1, sub0))), sub0,
+    (V_ALIGNBIT_B32_e64
+      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)),
+      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)), 
+      (i32 (EXTRACT_SUBREG VReg_64:$src1, sub1))), sub1)
+>;
+
+// Prevents regression in fneg-modifier-casting.ll along with modifications to XorCombine() when v2i32 or is legal.
+def : AMDGPUPat <
+  (fneg (select i1:$src0, (f32 (bitconvert i32:$src1)), (f32 (bitconvert i32:$src2)))),
+    (V_CNDMASK_B32_e64 (i32 1), $src2, (i32 1), $src1, $src0)>;
----------------
chrisjbris wrote:

I'm working on modifying foldFreeOpFromSelect so that it is not applied in this case e.g. 

```
// select c, (fneg (bitcast x)), (fneg (bitcast y)) can be lowered
    // directly to a V_CNDMASK_. So prevent the fneg from being pulled
    // out in this case.
    if (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG) {
      SDValue LHSFNeg = LHS.getOperand(0);
      SDValue RHSFNeg = RHS.getOperand(0);
      if (LHSFNeg.getOpcode() == ISD::BITCAST &&
          RHSFNeg->getOpcode() == ISD::BITCAST)
        return SDValue();
    }
```

This works for fneg-modifier-casting.ll but causes a mixture of codegen improvements and regressions in fneg-combines.new.ll

https://github.com/llvm/llvm-project/pull/140694