[llvm] [AMDGPU] New RegBankSelect: Map P0 to B64 (PR #142560)

[Petar Avramovic via llvm-commits]

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@@ -203,8 +203,8 @@ UniformityLLTOpPredicateID LLTToBId(LLT Ty) {
       Ty == LLT::pointer(6, 32))
     return B32;
   if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
-      Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(1, 64) ||
-      Ty == LLT::pointer(4, 64) ||
+      Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(0, 64) ||
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petar-avramovic wrote:

The original intent was to have a clear list of all types that can appear in type check generated from tablegen in instruction select.
`Ty.getSizeInBits() == 64` also works if you find it more appropriate

https://github.com/llvm/llvm-project/pull/142560