[llvm] [llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (PR #142529)

Lakshay Kumar via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 3 00:46:43 PDT 2025


================
@@ -229,6 +233,40 @@ class ExegesisAArch64Target : public ExegesisTarget {
   }
 };
 
+Error ExegesisAArch64Target::randomizeTargetMCOperand(
+    const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
+    const BitVector &ForbiddenRegs) const {
+  const Operand &Op = Instr.getPrimaryOperand(Var);
+  const auto OperandType = Op.getExplicitOperandInfo().OperandType;
+  // Introducing some illegal instructions for (15) a few opcodes
+  // TODO: Look into immediate values to be opcode specific
+  switch (OperandType) {
+    case MCOI::OperandType::OPERAND_UNKNOWN: {
+      unsigned Opcode = Instr.getOpcode();
+      switch (Opcode) {
+        case AArch64::MOVIv2s_msl:
+        case AArch64::MOVIv4s_msl:
+        case AArch64::MVNIv2s_msl:
+        case AArch64::MVNIv4s_msl:
+          AssignedValue = MCOperand::createImm(8); // or 16, as needed
----------------
lakshayk-nv wrote:

`msl` opcode asset for immediate values being 8 or 16. [Here](https://llvm.org/doxygen/AArch64MCCodeEmitter_8cpp_source.html#:~:text=assert((ShiftVal%20%3D%3D%208,705)

https://github.com/llvm/llvm-project/pull/142529


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