[llvm] [AArch64] Extend usage of `XAR` instruction for fixed-length operations (PR #139460)

[David Green via llvm-commits]

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@@ -4632,22 +4632,55 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
   SDValue Imm = CurDAG->getTargetConstant(
       ShAmt, DL, N0.getOperand(1).getValueType(), false);
 
-  if (ShAmt + HsAmt != 64)
+  unsigned VTSizeInBits =
+      (Subtarget->hasSVE2() ? VT.getScalarSizeInBits() : 64);
+  if (ShAmt + HsAmt != VTSizeInBits)
     return false;
 
+  // We have Neon SHA3 XAR operation for v2i64 but for types
+  // v4i32, v8i16, v16i8 we can use SVE operations when SVE2-SHA3
+  // is available.
+  EVT SVT = MVT::v2i64;
+  switch (VT.getSimpleVT().SimpleTy) {
+  case MVT::v4i32:
+    SVT = MVT::nxv4i32;
+    break;
+  case MVT::v8i16:
+    SVT = MVT::nxv8i16;
+    break;
+  case MVT::v16i8:
+    SVT = MVT::nxv16i8;
+    break;
+  default:
+    if (!(VT == MVT::v2i64 || VT == MVT::v1i64))
+      return false;
+    break;
+  }
+
   if (!IsXOROperand) {
     SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i64);
-    SDNode *MOV =
-        CurDAG->getMachineNode(AArch64::MOVIv2d_ns, DL, MVT::v2i64, Zero);
+    SDNode *MOV = CurDAG->getMachineNode(AArch64::MOVIv2d_ns, DL, SVT, Zero);
     SDValue MOVIV = SDValue(MOV, 0);
+
     R1 = N1->getOperand(0);
     R2 = MOVIV;
   }
 
+  if (SVT != VT && VT != MVT::v1i64) {
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davemgreen wrote:

SVT.isScalableVector() maybe?

https://github.com/llvm/llvm-project/pull/139460