[llvm] [llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (PR #142529)

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index 0a99bb961..b6c405806 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -115,9 +115,9 @@ public:
   ExegesisAArch64Target()
       : ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {}
 
-  Error randomizeTargetMCOperand(
-      const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
-      const BitVector &ForbiddenRegs) const override;
+  Error randomizeTargetMCOperand(const Instruction &Instr, const Variable &Var,
+                                 MCOperand &AssignedValue,
+                                 const BitVector &ForbiddenRegs) const override;
 
 private:
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
@@ -165,25 +165,25 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
   // Introducing some illegal instructions for (15) a few opcodes
   // TODO: Look into immediate values to be opcode specific
   switch (OperandType) {
-    case MCOI::OperandType::OPERAND_UNKNOWN: {
-      unsigned Opcode = Instr.getOpcode();
-      switch (Opcode) {
-        case AArch64::MOVIv2s_msl:
-        case AArch64::MOVIv4s_msl:
-        case AArch64::MVNIv2s_msl:
-        case AArch64::MVNIv4s_msl:
-          AssignedValue = MCOperand::createImm(8); // or 16, as needed
-          return Error::success();
-        default:
-          AssignedValue = MCOperand::createImm(0);
-          return Error::success();
-      }
-    }
-    case MCOI::OperandType::OPERAND_PCREL:
-      AssignedValue = MCOperand::createImm(0);
+  case MCOI::OperandType::OPERAND_UNKNOWN: {
+    unsigned Opcode = Instr.getOpcode();
+    switch (Opcode) {
+    case AArch64::MOVIv2s_msl:
+    case AArch64::MOVIv4s_msl:
+    case AArch64::MVNIv2s_msl:
+    case AArch64::MVNIv4s_msl:
+      AssignedValue = MCOperand::createImm(8); // or 16, as needed
       return Error::success();
     default:
-      break;
+      AssignedValue = MCOperand::createImm(0);
+      return Error::success();
+    }
+  }
+  case MCOI::OperandType::OPERAND_PCREL:
+    AssignedValue = MCOperand::createImm(0);
+    return Error::success();
+  default:
+    break;
   }
 
   return make_error<Failure>(
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index d4381c3b1..6859a9d49 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -276,7 +276,8 @@ static Error randomizeMCOperand(const LLVMState &State,
     AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));
     break;
   }
-  /// Omit unknown and pc-relative operands to imm value based on the instruction
+  /// Omit unknown and pc-relative operands to imm value based on the
+  /// instruction
   // TODO: Neccesity of AArch64 guard ?
 #ifdef __aarch64__
   case MCOI::OperandType::OPERAND_UNKNOWN:

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https://github.com/llvm/llvm-project/pull/142529