[llvm] [LoongArch] Lower vector select mask generation to `[X]VMSK{LT,GE,NE}Z` if possible (PR #142109)

[via llvm-commits]

heiher wrote:

> For byte we have `>=0` and `!=0`, they can combine to `>0`.

We also have `V{SEQ, SLE, SLT}`, the next is to support combinations with `VMSK{LT, GE, NE}`. For example, the expression `x > 0` can be transformed as:

not (x <= 0)

```asm
vslei.b t, x, 0
vmskgez.b t, t
```

https://github.com/llvm/llvm-project/pull/142109