[llvm] [SelectionDAG][AArch64] Legalize power of 2 vector.[de]interleaveN (PR #141513)

[Paul Walker via llvm-commits]

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@@ -3558,6 +3558,59 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
     Results.push_back(TLI.expandVectorSplice(Node, DAG));
     break;
   }
+  case ISD::VECTOR_DEINTERLEAVE: {
+    unsigned Factor = Node->getNumOperands();
+    if (Factor <= 2 || !isPowerOf2_32(Factor))
+      break;
+    SmallVector<SDValue, 8> Ops;
+    for (SDValue Op : Node->ops())
+      Ops.push_back(Op);
+    EVT VecVT = Node->getValueType(0);
+    SmallVector<EVT> HalfVTs(Factor / 2, VecVT);
+    // Deinterleave at Factor/2 so each result contains two factors interleaved:
+    // ab cd ab cd -> [ac bd] [ac bd]
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paulwalker-arm wrote:

For this and the related comments it would be better to use unique letters throughout to make it clearer all lanes are distinct.

https://github.com/llvm/llvm-project/pull/141513