[llvm] [PowerPC] Remove carry register (PR #142420)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 2 08:59:05 PDT 2025
https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/142420
In practice this register is indistinguishable from xer, so remove it
and use xer throughout.
>From 5fa65765538d99bc5a0bf21b95bb21a41570bd3e Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Mon, 2 Jun 2025 16:52:51 +0100
Subject: [PATCH] [PowerPC] Remove carry register
In practice this register is indistinguishable from xer, so remove it
and use xer throughout.
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +-
llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 20 +++----
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 8 +--
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 48 +++++++--------
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +-
llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 9 +--
llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll | 58 +++++++++----------
.../CodeGen/PowerPC/aix-cc-byval-split.ll | 4 +-
.../carry-liveness-after-expand-isel.ll | 16 ++---
.../CodeGen/PowerPC/convert-ri-addi-to-ri.mir | 6 +-
.../convert-rr-to-ri-instrs-out-of-range.mir | 16 ++---
.../PowerPC/convert-rr-to-ri-instrs.mir | 40 ++++++-------
.../PowerPC/ctrloop-do-not-duplicate-mi.mir | 2 +-
.../test/CodeGen/PowerPC/early-ret-verify.mir | 8 +--
llvm/test/CodeGen/PowerPC/ifcvt.mir | 4 +-
.../CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 6 +-
16 files changed, 123 insertions(+), 130 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 0c2a506005604..02e0df26b9c13 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13633,9 +13633,9 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
- if (isPhysRegUsedAfter(PPC::CARRY, MI.getIterator())) {
- copy0MBB->addLiveIn(PPC::CARRY);
- sinkMBB->addLiveIn(PPC::CARRY);
+ if (isPhysRegUsedAfter(PPC::XER, MI.getIterator())) {
+ copy0MBB->addLiveIn(PPC::XER);
+ sinkMBB->addLiveIn(PPC::XER);
}
// Set the call frame size on entry to the new basic blocks.
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 659c1a9079c33..32c86ad0b5ea1 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -763,7 +763,7 @@ defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
[(set i64:$RT, (PPCaddc i64:$RA, i64:$RB))]>,
PPC970_DGroup_Cracked;
-let Defs = [CARRY] in
+let Defs = [XER] in
def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
"addic $RST, $RA, $D", IIC_IntGeneral,
[(set i64:$RST, (PPCaddc i64:$RA, imm64SExt16:$D))]>;
@@ -779,7 +779,7 @@ def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
[(set i64:$RST, (add i64:$RA,
(PPClo tglobaladdr:$D, 0)))]>, MemriOp;
-let Defs = [CARRY] in {
+let Defs = [XER] in {
def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
"subfic $RST, $RA, $D", IIC_IntGeneral,
[(set i64:$RST, (PPCsubc imm64SExt16:$D, i64:$RA))]>;
@@ -794,26 +794,26 @@ defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"neg", "$RT, $RA", IIC_IntSimple,
[(set i64:$RT, (ineg i64:$RA))]>;
-let Uses = [CARRY] in {
+let Uses = [XER] in {
let isCommutable = 1 in
defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"adde", "$RT, $RA, $RB", IIC_IntGeneral,
- [(set i64:$RT, (PPCadde i64:$RA, i64:$RB, CARRY))]>;
+ [(set i64:$RT, (PPCadde i64:$RA, i64:$RB, XER))]>;
defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"addme", "$RT, $RA", IIC_IntGeneral,
- [(set i64:$RT, (PPCadde i64:$RA, -1, CARRY))]>;
+ [(set i64:$RT, (PPCadde i64:$RA, -1, XER))]>;
defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"addze", "$RT, $RA", IIC_IntGeneral,
- [(set i64:$RT, (PPCadde i64:$RA, 0, CARRY))]>;
+ [(set i64:$RT, (PPCadde i64:$RA, 0, XER))]>;
defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"subfe", "$RT, $RA, $RB", IIC_IntGeneral,
- [(set i64:$RT, (PPCsube i64:$RB, i64:$RA, CARRY))]>;
+ [(set i64:$RT, (PPCsube i64:$RB, i64:$RA, XER))]>;
defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"subfme", "$RT, $RA", IIC_IntGeneral,
- [(set i64:$RT, (PPCsube -1, i64:$RA, CARRY))]>;
+ [(set i64:$RT, (PPCsube -1, i64:$RA, XER))]>;
defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"subfze", "$RT, $RA", IIC_IntGeneral,
- [(set i64:$RT, (PPCsube 0, i64:$RA, CARRY))]>;
+ [(set i64:$RT, (PPCsube 0, i64:$RA, XER))]>;
}
} // isCodeGenOnly
@@ -983,7 +983,7 @@ defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH),
[]>, isPPC64, Requires<[IsISA3_0]>;
// For fast-isel:
-let isCodeGenOnly = 1, Defs = [CARRY] in
+let isCodeGenOnly = 1, Defs = [XER] in
def SRADI_32 : XSForm_1<31, 413, (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH),
"sradi $RA, $RS, $SH", IIC_IntRotateDI, []>, isPPC64;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 9d4d2d864fc32..99b6dd03f25c5 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1760,20 +1760,20 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
} else if ((PPC::G8RCRegClass.contains(DestReg) ||
PPC::GPRCRegClass.contains(DestReg)) &&
- SrcReg == PPC::CARRY) {
+ SrcReg == PPC::XER) {
bool Is64Bit = PPC::G8RCRegClass.contains(DestReg);
BuildMI(MBB, I, DL, get(Is64Bit ? PPC::MFSPR8 : PPC::MFSPR), DestReg)
.addImm(1)
- .addReg(PPC::CARRY, RegState::Implicit);
+ .addReg(PPC::XER, RegState::Implicit);
return;
} else if ((PPC::G8RCRegClass.contains(SrcReg) ||
PPC::GPRCRegClass.contains(SrcReg)) &&
- DestReg == PPC::CARRY) {
+ DestReg == PPC::XER) {
bool Is64Bit = PPC::G8RCRegClass.contains(SrcReg);
BuildMI(MBB, I, DL, get(Is64Bit ? PPC::MTSPR8 : PPC::MTSPR))
.addImm(1)
.addReg(SrcReg)
- .addReg(PPC::CARRY, RegState::ImplicitDefine);
+ .addReg(PPC::XER, RegState::ImplicitDefine);
return;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index b70290df07b1c..3a8a9a7c413b8 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -789,11 +789,11 @@ multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> {
let BaseName = asmbase in {
- let Defs = [CARRY] in
+ let Defs = [XER] in
def NAME : XForm_6<opcode, xo, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
pattern>, RecFormRel;
- let Defs = [CARRY, CR0] in
+ let Defs = [XER, CR0] in
def _rec : XForm_6<opcode, xo, OOL, IOL,
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
[]>, isRecordForm, RecFormRel;
@@ -804,11 +804,11 @@ multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> {
let BaseName = asmbase in {
- let Defs = [CARRY] in
+ let Defs = [XER] in
def NAME : XForm_10<opcode, xo, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
pattern>, RecFormRel;
- let Defs = [CARRY, CR0] in
+ let Defs = [XER, CR0] in
def _rec : XForm_10<opcode, xo, OOL, IOL,
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
[]>, isRecordForm, RecFormRel;
@@ -900,21 +900,21 @@ multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> {
let BaseName = asmbase in {
- let Defs = [CARRY] in
+ let Defs = [XER] in
def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
pattern>, RecFormRel;
- let Defs = [CARRY, CR0] in
+ let Defs = [XER, CR0] in
def _rec : XOForm_1<opcode, xo, oe, OOL, IOL,
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
[]>, isRecordForm, RecFormRel;
}
let BaseName = !strconcat(asmbase, "O") in {
- let Defs = [CARRY, XER] in
+ let Defs = [XER] in
def O : XOForm_1<opcode, xo, 1, OOL, IOL,
!strconcat(asmbase, !strconcat("o ", asmstr)), itin,
[]>, RecFormRel;
- let Defs = [CARRY, XER, CR0] in
+ let Defs = [XER, CR0] in
def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL,
!strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
[]>, isRecordForm, RecFormRel;
@@ -949,21 +949,21 @@ multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> {
let BaseName = asmbase in {
- let Defs = [CARRY] in
+ let Defs = [XER] in
def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
pattern>, RecFormRel;
- let Defs = [CARRY, CR0] in
+ let Defs = [XER, CR0] in
def _rec : XOForm_3<opcode, xo, oe, OOL, IOL,
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
[]>, isRecordForm, RecFormRel;
}
let BaseName = !strconcat(asmbase, "O") in {
- let Defs = [CARRY, XER] in
+ let Defs = [XER] in
def O : XOForm_3<opcode, xo, 1, OOL, IOL,
!strconcat(asmbase, !strconcat("o ", asmstr)), itin,
[]>, RecFormRel;
- let Defs = [CARRY, XER, CR0] in
+ let Defs = [XER, CR0] in
def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL,
!strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
[]>, isRecordForm, RecFormRel;
@@ -1030,11 +1030,11 @@ multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> {
let BaseName = asmbase in {
- let Defs = [CARRY] in
+ let Defs = [XER] in
def NAME : XSForm_1<opcode, xo, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
pattern>, RecFormRel;
- let Defs = [CARRY, CR0] in
+ let Defs = [XER, CR0] in
def _rec : XSForm_1<opcode, xo, OOL, IOL,
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
[]>, isRecordForm, RecFormRel;
@@ -2312,12 +2312,12 @@ def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),
"addi $RST, $RA, $D", IIC_IntSimple,
[(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>;
let BaseName = "addic" in {
-let Defs = [CARRY] in
+let Defs = [XER] in
def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
"addic $RST, $RA, $D", IIC_IntGeneral,
[(set i32:$RST, (PPCaddc i32:$RA, imm32SExt16:$D))]>,
RecFormRel, PPC970_DGroup_Cracked;
-let Defs = [CARRY, CR0] in
+let Defs = [XER, CR0] in
def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
"addic. $RST, $RA, $D", IIC_IntGeneral,
[]>, isRecordForm, RecFormRel;
@@ -2333,7 +2333,7 @@ def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),
def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
"mulli $RST, $RA, $D", IIC_IntMulLI,
[(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>;
-let Defs = [CARRY] in
+let Defs = [XER] in
def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
"subfic $RST, $RA, $D", IIC_IntGeneral,
[(set i32:$RST, (PPCsubc imm32SExt16:$D, i32:$RA))]>;
@@ -2971,26 +2971,26 @@ defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA),
"neg", "$RT, $RA", IIC_IntSimple,
[(set i32:$RT, (ineg i32:$RA))]>;
-let Uses = [CARRY] in {
+let Uses = [XER] in {
let isCommutable = 1 in
defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"adde", "$RT, $RA, $RB", IIC_IntGeneral,
- [(set i32:$RT, (PPCadde i32:$RA, i32:$RB, CARRY))]>;
+ [(set i32:$RT, (PPCadde i32:$RA, i32:$RB, XER))]>;
defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA),
"addme", "$RT, $RA", IIC_IntGeneral,
- [(set i32:$RT, (PPCadde i32:$RA, -1, CARRY))]>;
+ [(set i32:$RT, (PPCadde i32:$RA, -1, XER))]>;
defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA),
"addze", "$RT, $RA", IIC_IntGeneral,
- [(set i32:$RT, (PPCadde i32:$RA, 0, CARRY))]>;
+ [(set i32:$RT, (PPCadde i32:$RA, 0, XER))]>;
defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"subfe", "$RT, $RA, $RB", IIC_IntGeneral,
- [(set i32:$RT, (PPCsube i32:$RB, i32:$RA, CARRY))]>;
+ [(set i32:$RT, (PPCsube i32:$RB, i32:$RA, XER))]>;
defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA),
"subfme", "$RT, $RA", IIC_IntGeneral,
- [(set i32:$RT, (PPCsube -1, i32:$RA, CARRY))]>;
+ [(set i32:$RT, (PPCsube -1, i32:$RA, XER))]>;
defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA),
"subfze", "$RT, $RA", IIC_IntGeneral,
- [(set i32:$RT, (PPCsube 0, i32:$RA, CARRY))]>;
+ [(set i32:$RT, (PPCsube 0, i32:$RA, XER))]>;
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 51902ad218d1c..1fa62b5e8d534 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -627,7 +627,7 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
const TargetRegisterClass *
PPCRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
- if (RC == &PPC::CARRYRCRegClass)
+ if (RC == &PPC::XERRCRegClass)
return TM.isPPC64() ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
return RC;
}
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 359adc31eb10b..1a39336dc7a20 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -307,13 +307,6 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
-// Carry bit. In the architecture this is really bit 0 of the XER register
-// (which really is SPR register 1); this is the only bit interesting to a
-// compiler.
-def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {
- let Aliases = [XER];
-}
-
// FP rounding mode: bits 30 and 31 of the FP status and control register
// This is not allocated as a normal register; it appears only in
// Uses and Defs. The ABI says it needs to be preserved by a function,
@@ -492,7 +485,7 @@ def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> {
}
def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
-def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
+def XERRC : RegisterClass<"PPC", [i32], 32, (add XER)> {
let CopyCost = -1;
let isAllocatable = 0;
}
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
index aead5762d0921..a66224ec96b1e 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
@@ -301,12 +301,12 @@ define i64 @test_i64(i64 %a, i64 %b, i64 %c, i64 %d) {
; 32BIT: bb.0.entry:
; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
; 32BIT-NEXT: {{ $}}
- ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r6, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r5, implicit-def dead $carry, implicit killed $carry
- ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r8, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r7, implicit-def dead $carry, implicit killed $carry
- ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r10, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r9, implicit-def dead $carry, implicit killed $carry
+ ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r6, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r5, implicit-def dead $xer, implicit killed $xer
+ ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r8, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r7, implicit-def dead $xer, implicit killed $xer
+ ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r10, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r9, implicit-def dead $xer, implicit killed $xer
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4
;
; 64BIT-LABEL: name: test_i64
@@ -678,9 +678,9 @@ define i64 @callee_mixed_ints(i32 %a, i8 signext %b, i32 %c, i16 signext %d, i64
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6
- ; 32BIT-NEXT: renamable $r5 = SRAWI renamable $r3, 31, implicit-def dead $carry
- ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r3, killed renamable $r8, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r5, killed renamable $r7, implicit-def dead $carry, implicit killed $carry
+ ; 32BIT-NEXT: renamable $r5 = SRAWI renamable $r3, 31, implicit-def dead $xer
+ ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r3, killed renamable $r8, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r5, killed renamable $r7, implicit-def dead $xer, implicit killed $xer
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4
;
; 64BIT-LABEL: name: callee_mixed_ints
@@ -1113,30 +1113,30 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6
- ; 32BIT-NEXT: renamable $r5 = SRAWI renamable $r11, 31, implicit-def dead $carry
- ; 32BIT-NEXT: renamable $r4 = SRAWI renamable $r12, 31, implicit-def dead $carry
+ ; 32BIT-NEXT: renamable $r5 = SRAWI renamable $r11, 31, implicit-def dead $xer
+ ; 32BIT-NEXT: renamable $r4 = SRAWI renamable $r12, 31, implicit-def dead $xer
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r7
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r8
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r9
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r10
- ; 32BIT-NEXT: renamable $r6 = SRAWI renamable $r3, 31, implicit-def dead $carry
- ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r25, implicit-def $carry
- ; 32BIT-NEXT: renamable $r6 = ADDE killed renamable $r6, killed renamable $r26, implicit-def dead $carry, implicit $carry
- ; 32BIT-NEXT: renamable $r7 = SRAWI renamable $r27, 31, implicit-def dead $carry
- ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r27, implicit-def $carry
- ; 32BIT-NEXT: renamable $r6 = ADDE killed renamable $r6, killed renamable $r7, implicit-def dead $carry, implicit $carry
- ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r28, implicit-def $carry
- ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r6, implicit-def dead $carry, implicit $carry
- ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r29, implicit-def $carry
- ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r6, implicit-def dead $carry, implicit $carry
- ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r12, implicit-def $carry
- ; 32BIT-NEXT: renamable $r4 = ADDE killed renamable $r6, killed renamable $r4, implicit-def dead $carry, implicit $carry
- ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r30, implicit-def $carry
- ; 32BIT-NEXT: renamable $r4 = ADDE killed renamable $r4, killed renamable $r31, implicit-def dead $carry, implicit $carry
- ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r0, implicit-def $carry
- ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r4, implicit-def dead $carry, implicit $carry
- ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r3, killed renamable $r11, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r6, killed renamable $r5, implicit-def dead $carry, implicit $carry
+ ; 32BIT-NEXT: renamable $r6 = SRAWI renamable $r3, 31, implicit-def dead $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r25, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r6 = ADDE killed renamable $r6, killed renamable $r26, implicit-def dead $xer, implicit $xer
+ ; 32BIT-NEXT: renamable $r7 = SRAWI renamable $r27, 31, implicit-def dead $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r27, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r6 = ADDE killed renamable $r6, killed renamable $r7, implicit-def dead $xer, implicit $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r28, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r6, implicit-def dead $xer, implicit $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r29, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r6, implicit-def dead $xer, implicit $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r12, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r4 = ADDE killed renamable $r6, killed renamable $r4, implicit-def dead $xer, implicit $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r30, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r4 = ADDE killed renamable $r4, killed renamable $r31, implicit-def dead $xer, implicit $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDC killed renamable $r3, killed renamable $r0, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r6 = ADDZE killed renamable $r4, implicit-def dead $xer, implicit $xer
+ ; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r3, killed renamable $r11, implicit-def $xer
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r6, killed renamable $r5, implicit-def dead $xer, implicit $xer
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4
;
; 64BIT-LABEL: name: test_ints_stack
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
index 9b1893b111556..44d00711e8dc0 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
@@ -45,8 +45,8 @@ entry:
; CHECK32-DAG: STW renamable $r7, 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16
; CHECK32-DAG: STW renamable $r8, 20, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 20
; CHECK32-DAG: STW killed renamable $r9, 24, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 24
-; CHECK32: renamable $r4 = ADDC killed renamable $r8, killed renamable $r[[REG2]], implicit-def $carry
-; CHECK32: renamable $r3 = ADDE killed renamable $r7, killed renamable $r[[REG1]], implicit-def dead $carry, implicit killed $carry
+; CHECK32: renamable $r4 = ADDC killed renamable $r8, killed renamable $r[[REG2]], implicit-def $xer
+; CHECK32: renamable $r3 = ADDE killed renamable $r7, killed renamable $r[[REG1]], implicit-def dead $xer, implicit killed $xer
; CHECK32 STW killed renamable $r10, 28, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 28
; CHECK32: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4
diff --git a/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll b/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
index 15ab8aa05b329..f315c7d0eac90 100644
--- a/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
@@ -17,7 +17,7 @@ define i32 @md_seq_show(i64 %0, i32 %1) #0 {
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY $r3
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]]
- ; CHECK-NEXT: [[ADDIC:%[0-9]+]]:gprc = ADDIC [[COPY1]], 1, implicit-def $carry
+ ; CHECK-NEXT: [[ADDIC:%[0-9]+]]:gprc = ADDIC [[COPY1]], 1, implicit-def $xer
; CHECK-NEXT: [[CMPLWI:%[0-9]+]]:crrc = CMPLWI killed [[ADDIC]], 1
; CHECK-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 0
; CHECK-NEXT: [[LI1:%[0-9]+]]:gprc_and_gprc_nor0 = LI 1
@@ -25,16 +25,16 @@ define i32 @md_seq_show(i64 %0, i32 %1) #0 {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.entry:
; CHECK-NEXT: successors: %bb.4(0x80000000)
- ; CHECK-NEXT: liveins: $carry
+ ; CHECK-NEXT: liveins: $xer
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.entry:
; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
- ; CHECK-NEXT: liveins: $carry
+ ; CHECK-NEXT: liveins: $xer
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gprc_and_gprc_nor0 = PHI [[LI]], %bb.3, [[LI1]], %bb.0
- ; CHECK-NEXT: [[ADDZE:%[0-9]+]]:gprc = ADDZE [[COPY2]], implicit-def dead $carry, implicit $carry
- ; CHECK-NEXT: [[ADDIC1:%[0-9]+]]:gprc = ADDIC [[ADDZE]], -1, implicit-def $carry
- ; CHECK-NEXT: [[SUBFE:%[0-9]+]]:gprc_and_gprc_nor0 = SUBFE killed [[ADDIC1]], [[ADDZE]], implicit-def dead $carry, implicit $carry
+ ; CHECK-NEXT: [[ADDZE:%[0-9]+]]:gprc = ADDZE [[COPY2]], implicit-def dead $xer, implicit $xer
+ ; CHECK-NEXT: [[ADDIC1:%[0-9]+]]:gprc = ADDIC [[ADDZE]], -1, implicit-def $xer
+ ; CHECK-NEXT: [[SUBFE:%[0-9]+]]:gprc_and_gprc_nor0 = SUBFE killed [[ADDIC1]], [[ADDZE]], implicit-def dead $xer, implicit $xer
; CHECK-NEXT: [[CMPLWI1:%[0-9]+]]:crrc = CMPLWI [[ADDZE]], 0
; CHECK-NEXT: BCC 76, [[CMPLWI1]], %bb.6
; CHECK-NEXT: {{ $}}
@@ -55,8 +55,8 @@ define i32 @md_seq_show(i64 %0, i32 %1) #0 {
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.status_resync.exit:
- ; CHECK-NEXT: [[ADDIC2:%[0-9]+]]:gprc = ADDIC [[COPY]], -1, implicit-def $carry
- ; CHECK-NEXT: [[SUBFE1:%[0-9]+]]:gprc = SUBFE killed [[ADDIC2]], [[COPY]], implicit-def dead $carry, implicit $carry
+ ; CHECK-NEXT: [[ADDIC2:%[0-9]+]]:gprc = ADDIC [[COPY]], -1, implicit-def $xer
+ ; CHECK-NEXT: [[SUBFE1:%[0-9]+]]:gprc = SUBFE killed [[ADDIC2]], [[COPY]], implicit-def dead $xer, implicit $xer
; CHECK-NEXT: [[LIS:%[0-9]+]]:gprc_and_gprc_nor0 = LIS target-flags(ppc-ha) @md_seq_show___trans_tmp_57
; CHECK-NEXT: STB killed [[SUBFE1]], target-flags(ppc-lo) @md_seq_show___trans_tmp_57, killed [[LIS]] :: (store (s8) into @md_seq_show___trans_tmp_57)
; CHECK-NEXT: [[LI3:%[0-9]+]]:gprc = LI 0
diff --git a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
index 2432f4245b46d..49c7523ec7a98 100644
--- a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
@@ -58,9 +58,9 @@ body: |
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc = ADDI8 %0:g8rc_and_g8rc_nox0, 1
%2:g8rc = LI8 1
- ; CHECK: SUBFIC8 killed %1, 1, implicit-def $carry
- %3:g8rc = SUBFC8 killed %1:g8rc, %2:g8rc, implicit-def $carry
- %4:g8rc = SUBFE8 %2:g8rc, %2:g8rc, implicit-def dead $carry, implicit $carry
+ ; CHECK: SUBFIC8 killed %1, 1, implicit-def $xer
+ %3:g8rc = SUBFC8 killed %1:g8rc, %2:g8rc, implicit-def $xer
+ %4:g8rc = SUBFE8 %2:g8rc, %2:g8rc, implicit-def dead $xer, implicit $xer
%5:g8rc = NEG8 killed %4:g8rc
$x3 = COPY %5:g8rc
BLR8 implicit $lr8, implicit $rm, implicit $x3
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
index cdd6be56b46d5..9e3d0668d27a1 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
@@ -720,9 +720,9 @@ body: |
%0 = COPY $x3
%2 = LI 48
%3 = COPY %0.sub_32
- %4 = SRAW killed %3, killed %2, implicit-def dead $carry
+ %4 = SRAW killed %3, killed %2, implicit-def dead $xer
; CHECK: LI 48
- ; CHECK: SRAW8 killed %7, killed %9, implicit-def $carry, implicit-def dead $carry
+ ; CHECK: SRAW8 killed %7, killed %9, implicit-def $xer, implicit-def dead $xer
; CHECK-LATE: sraw 3, 3, 4
%5 = EXTSW_32_64 killed %4
$x3 = COPY %5
@@ -778,8 +778,8 @@ body: |
%0 = COPY $x3
%2 = LI 80
%3 = COPY %0.sub_32
- %4 = SRAW_rec killed %3, %2, implicit-def dead $carry, implicit-def $cr0
- ; CHECK: SRAW8_rec killed %10, killed %12, implicit-def $carry, implicit-def $cr0, implicit-def dead $carry, implicit-def $cr0
+ %4 = SRAW_rec killed %3, %2, implicit-def dead $xer, implicit-def $cr0
+ ; CHECK: SRAW8_rec killed %10, killed %12, implicit-def $xer, implicit-def $cr0, implicit-def dead $xer, implicit-def $cr0
; CHECK-LATE: sraw. 3, 3, 4
%5 = COPY killed $cr0
%6 = ISEL %2, %4, %5.sub_eq
@@ -1264,8 +1264,8 @@ body: |
%1 = COPY $x4
%0 = COPY $x3
%2 = LI -44
- %3 = SRAD %0, killed %2, implicit-def dead $carry
- ; CHECK: SRAD killed %0, killed %2, implicit-def dead $carry
+ %3 = SRAD %0, killed %2, implicit-def dead $xer
+ ; CHECK: SRAD killed %0, killed %2, implicit-def dead $xer
; CHECK-LATE: srad 3, 3, 4
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1317,8 +1317,8 @@ body: |
%1 = COPY $x4
%0 = COPY $x3
%2 = LI 68
- %3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
- ; CHECK: SRAD_rec killed %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+ %3 = SRAD_rec %0, killed %2, implicit-def dead $xer, implicit-def $cr0
+ ; CHECK: SRAD_rec killed %0, killed %2, implicit-def dead $xer, implicit-def $cr0
; CHECK-LATE: srad. 3, 3, 5
%4 = COPY killed $cr0
%5 = ISEL8 %1, %3, %4.sub_eq
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
index fa06dd551a0d4..eeaa43598ed41 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -1175,10 +1175,10 @@ body: |
%0 = COPY $x3
%4 = COPY %0.sub_32
%5 = LI 55
- %6 = ADDC %5, %4, implicit-def $carry
- ; CHECK: ADDIC killed %4, 55, implicit-def $carry
+ %6 = ADDC %5, %4, implicit-def $xer
+ ; CHECK: ADDIC killed %4, 55, implicit-def $xer
; CHECK-LATE: addic 3, 3, 55
- %7 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
+ %7 = ADDE8 %3, %1, implicit-def dead $xer, implicit $xer
%8 = EXTSW_32_64 %6
$x3 = COPY %8
$x4 = COPY %7
@@ -1234,10 +1234,10 @@ body: |
%2 = COPY $x5
%1 = COPY $x4
%0 = LI8 777
- %4 = ADDC8 %2, %0, implicit-def $carry
- ; CHECK: ADDIC8 killed %2, 777, implicit-def $carry
+ %4 = ADDC8 %2, %0, implicit-def $xer
+ ; CHECK: ADDIC8 killed %2, 777, implicit-def $xer
; CHECK-LATE: addic 3, 5, 777
- %5 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
+ %5 = ADDE8 %3, %1, implicit-def dead $xer, implicit $xer
$x3 = COPY %4
$x4 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
@@ -1292,8 +1292,8 @@ body: |
%1 = LI 433
%0 = COPY $x3
%2 = COPY %0.sub_32
- %3 = ADDC_rec %1, %2, implicit-def $cr0, implicit-def $carry
- ; CHECK: ADDIC_rec killed %2, 433, implicit-def $cr0, implicit-def dead $carry
+ %3 = ADDC_rec %1, %2, implicit-def $cr0, implicit-def $xer
+ ; CHECK: ADDIC_rec killed %2, 433, implicit-def $cr0, implicit-def dead $xer
; CHECK-LATE: addic. 3, 3, 433
%4 = COPY killed $cr0
%5 = COPY %4.sub_eq
@@ -4989,10 +4989,10 @@ body: |
%0 = COPY $x3
%2 = LI 15
%3 = COPY %0.sub_32
- %4 = SRAW killed %3, killed %2, implicit-def dead $carry
+ %4 = SRAW killed %3, killed %2, implicit-def dead $xer
; CHECK: %6:g8rc = IMPLICIT_DEF
; CHECK-NEXT: %7:g8rc = INSERT_SUBREG %6, killed %3, %subreg.sub_32
- ; CHECK-NEXT: %8:g8rc = SRAWI8 killed %7, 15, implicit-def $carry, implicit-def dead $carry
+ ; CHECK-NEXT: %8:g8rc = SRAWI8 killed %7, 15, implicit-def $xer, implicit-def dead $xer
; CHECK-NEXT: %4:gprc = COPY killed %8.sub_32
; CHECK-LATE: srawi 3, 3, 15
%5 = EXTSW_32_64 killed %4
@@ -5049,8 +5049,8 @@ body: |
%0 = COPY $x3
%2 = LI 8
%3 = COPY %0.sub_32
- %4 = SRAW_rec killed %3, %2, implicit-def dead $carry, implicit-def $cr0
- ; CHECK: %11:g8rc = SRAWI8_rec killed %10, 8, implicit-def $carry, implicit-def $cr0, implicit-def dead $carry, implicit-def $cr0
+ %4 = SRAW_rec killed %3, %2, implicit-def dead $xer, implicit-def $cr0
+ ; CHECK: %11:g8rc = SRAWI8_rec killed %10, 8, implicit-def $xer, implicit-def $cr0, implicit-def dead $xer, implicit-def $cr0
; CHECK-LATE: srawi. 3, 3, 8
%5 = COPY killed $cr0
%6 = ISEL %2, %4, %5.sub_eq
@@ -5103,8 +5103,8 @@ body: |
%1 = COPY $x4
%0 = COPY $x3
%2 = LI 44
- %3 = SRAD %0, killed %2, implicit-def dead $carry
- ; CHECK: SRADI killed %0, 44, implicit-def dead $carry
+ %3 = SRAD %0, killed %2, implicit-def dead $xer
+ ; CHECK: SRADI killed %0, 44, implicit-def dead $xer
; CHECK-LATE: sradi 3, 3, 44
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -5156,8 +5156,8 @@ body: |
%1 = COPY $x4
%0 = COPY $x3
%2 = LI 61
- %3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
- ; CHECK: SRADI_rec killed %0, 61, implicit-def dead $carry, implicit-def $cr0
+ %3 = SRAD_rec %0, killed %2, implicit-def dead $xer, implicit-def $cr0
+ ; CHECK: SRADI_rec killed %0, 61, implicit-def dead $xer, implicit-def $cr0
; CHECK-LATE: sradi. 3, 3, 61
%4 = COPY killed $cr0
%5 = ISEL8 %1, %3, %4.sub_eq
@@ -6252,10 +6252,10 @@ body: |
%7 = COPY %2.sub_32
%8 = COPY %1.sub_32
%0 = LI 55
- %4 = SUBFC %7, %0, implicit-def $carry
+ %4 = SUBFC %7, %0, implicit-def $xer
; CHECK: SUBFIC killed %7, 55
; CHECK-LATE: subfic 3, 5, 55
- %5 = SUBFE %6, %8, implicit-def dead $carry, implicit $carry
+ %5 = SUBFE %6, %8, implicit-def dead $xer, implicit $xer
$x3 = EXTSW_32_64 %4
$x4 = EXTSW_32_64 %5
BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
@@ -6310,10 +6310,10 @@ body: |
%2 = COPY $x5
%1 = COPY $x4
%0 = LI8 7635
- %4 = SUBFC8 %2, %0, implicit-def $carry
+ %4 = SUBFC8 %2, %0, implicit-def $xer
; CHECK: SUBFIC8 killed %2, 7635
; CHECK-LATE: subfic 3, 5, 7635
- %5 = SUBFE8 %3, %1, implicit-def dead $carry, implicit $carry
+ %5 = SUBFE8 %3, %1, implicit-def dead $xer, implicit $xer
$x3 = COPY %4
$x4 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir b/llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir
index 651869d667380..7cddda16c4652 100644
--- a/llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir
+++ b/llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir
@@ -142,7 +142,7 @@ body: |
%8:gprc = LWZ 0, %9 :: (load (s32) from `ptr undef`)
%15:gprc = ANDI_rec %8, 1, implicit-def $cr0
%1:crbitrc = COPY $cr0eq
- %10:g8rc_and_g8rc_nox0 = SUBFIC8 %0, 1, implicit-def dead $carry
+ %10:g8rc_and_g8rc_nox0 = SUBFIC8 %0, 1, implicit-def dead $xer
%11:crrc = CMPDI %10, 1
%12:g8rc_and_g8rc_nox0 = LI8 1
%2:g8rc = ISEL8 %10, %12, %11.sub_gt
diff --git a/llvm/test/CodeGen/PowerPC/early-ret-verify.mir b/llvm/test/CodeGen/PowerPC/early-ret-verify.mir
index 967e53302607f..a9d715b1ef0a4 100644
--- a/llvm/test/CodeGen/PowerPC/early-ret-verify.mir
+++ b/llvm/test/CodeGen/PowerPC/early-ret-verify.mir
@@ -20,9 +20,9 @@ body: |
liveins: $r3, $r4
$r5 = OR $r4, $r4
- renamable $r4 = ADDIC killed $r4, 1, implicit-def $carry
+ renamable $r4 = ADDIC killed $r4, 1, implicit-def $xer
$r6 = OR $r3, $r3
- renamable $r3 = ADDZE killed $r3, implicit-def dead $carry, implicit killed $carry
+ renamable $r3 = ADDZE killed $r3, implicit-def dead $xer, implicit killed $xer
renamable $cr0 = CMPLW renamable $r3, killed renamable $r6
renamable $cr5lt = CRANDC renamable $cr0lt, renamable $cr0eq
renamable $cr1 = CMPLW renamable $r4, killed renamable $r5
@@ -46,9 +46,9 @@ body: |
; CHECK: renamable $r4 = IMPLICIT_DEF
; CHECK: bb.2:
; CHECK: $r5 = OR $r4, $r4
- ; CHECK: renamable $r4 = ADDIC killed $r4, 1, implicit-def $carry
+ ; CHECK: renamable $r4 = ADDIC killed $r4, 1, implicit-def $xer
; CHECK: $r6 = OR $r3, $r3
- ; CHECK: renamable $r3 = ADDZE killed $r3, implicit-def dead $carry, implicit killed $carry
+ ; CHECK: renamable $r3 = ADDZE killed $r3, implicit-def dead $xer, implicit killed $xer
; CHECK: renamable $cr0 = CMPLW renamable $r3, killed renamable $r6
; CHECK: renamable $cr5lt = CRANDC renamable $cr0lt, renamable $cr0eq
; CHECK: renamable $cr1 = CMPLW renamable $r4, killed renamable $r5
diff --git a/llvm/test/CodeGen/PowerPC/ifcvt.mir b/llvm/test/CodeGen/PowerPC/ifcvt.mir
index 3572ce83fc0eb..a2e02c45cf089 100644
--- a/llvm/test/CodeGen/PowerPC/ifcvt.mir
+++ b/llvm/test/CodeGen/PowerPC/ifcvt.mir
@@ -32,10 +32,10 @@ body: |
liveins: $r3, $r4, $r5
renamable $r6 = RLWINM renamable $r4, 3, 0, 28
- renamable $r4 = ADDIC killed renamable $r4, 1, implicit-def $carry
+ renamable $r4 = ADDIC killed renamable $r4, 1, implicit-def $xer
renamable $r5 = ADD4 killed renamable $r5, killed renamable $r6
renamable $r6 = ADD4 killed renamable $r6, renamable $r6
- renamable $r3 = ADDZE killed renamable $r3, implicit-def dead $carry, implicit $carry
+ renamable $r3 = ADDZE killed renamable $r3, implicit-def dead $xer, implicit $xer
BDZ %bb.5, implicit-def $ctr, implicit $ctr
bb.4:
diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
index 8140249cb3c7d..396caee47b312 100644
--- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
+++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
@@ -104,8 +104,8 @@ body: |
%1 = PHI %12, %bb.0.top, %5, %bb.3.loop
%2 = PHI %13, %bb.0.top, %4, %bb.3.loop
%3 = PHI %14, %bb.0.top, %5, %bb.3.loop
- %15 = SUBFC8 %3, %1, implicit-def $carry
- %16 = SUBFE8 %2, %0, implicit-def dead $carry, implicit $carry
+ %15 = SUBFC8 %3, %1, implicit-def $xer
+ %16 = SUBFE8 %2, %0, implicit-def dead $xer, implicit $xer
%17 = ADDI8 %16, -1
%18 = ADDI8 %15, -1
%19 = ANDC8 killed %17, %16
@@ -114,7 +114,7 @@ body: |
%24 = CNTLZD killed %20
%25 = CMPLDI %15, 0
BCC 76, %25, %bb.2.loop
- ; CHECK: SUBFC8_rec %3, %1, implicit-def $carry, implicit-def $cr0
+ ; CHECK: SUBFC8_rec %3, %1, implicit-def $xer, implicit-def $cr0
; CHECK: COPY killed $cr0
; CHECK: BCC
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