[llvm] [GlobalISel] Add G_CONCAT_VECTOR handling in computeNumSignBits (PR #142355)
Usha Gupta via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 2 03:17:30 PDT 2025
https://github.com/usha1830 created https://github.com/llvm/llvm-project/pull/142355
Code ported from SelectionDAG::ComputeNumSignBits
>From 88cbf677a92b5e5150d6098ea159211a822160ee Mon Sep 17 00:00:00 2001
From: Usha Gupta <usha.gupta at arm.com>
Date: Mon, 2 Jun 2025 10:12:03 +0000
Subject: [PATCH] [GlobalISel] Add G_CONCAT_VECTOR handling in
computeNumSignBits
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 21 ++++++++++
.../AArch64/GlobalISel/knownbits-concat.mir | 4 +-
.../AArch64/GlobalISel/legalize-min-max.mir | 40 ++++++++-----------
llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll | 2 -
llvm/test/CodeGen/AArch64/fcmp.ll | 18 ++++-----
llvm/test/CodeGen/AArch64/scmp.ll | 4 --
llvm/test/CodeGen/AArch64/ucmp.ll | 4 --
7 files changed, 46 insertions(+), 47 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 692befde71cb1..50c2f452ee18e 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -1958,6 +1958,27 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
}
break;
}
+ case TargetOpcode::G_CONCAT_VECTORS: {
+ if (MRI.getType(MI.getOperand(0).getReg()).isScalableVector())
+ break;
+ FirstAnswer = std::numeric_limits<unsigned>::max();
+ // Determine the minimum number of sign bits across all demanded
+ // elts of the input vectors. Early out if the result is already 1.
+ unsigned NumSubVectorElts =
+ MRI.getType(MI.getOperand(1).getReg()).getNumElements();
+ unsigned NumSubVectors = MI.getNumOperands() - 1;
+ for (unsigned i = 0; (i < NumSubVectors); ++i) {
+ APInt DemandedSub =
+ DemandedElts.extractBits(NumSubVectorElts, i * NumSubVectorElts);
+ if (!DemandedSub)
+ continue;
+ unsigned Tmp2 = computeNumSignBits(MI.getOperand(i + 1).getReg(),
+ DemandedSub, Depth + 1);
+
+ FirstAnswer = std::min(FirstAnswer, Tmp2);
+ }
+ break;
+ }
case TargetOpcode::G_SHUFFLE_VECTOR: {
// Collect the minimum number of sign bits that are shared by every vector
// element referenced by the shuffle.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-concat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-concat.mir
index 85129e9639a6a..03f7533c7d604 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-concat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-concat.mir
@@ -42,7 +42,7 @@ body: |
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %sext0:_ KnownBits:???????????????? SignBits:9
; CHECK-NEXT: %sext1:_ KnownBits:???????????????? SignBits:9
- ; CHECK-NEXT: %res:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %res:_ KnownBits:???????????????? SignBits:9
%0:_(<2 x s8>) = COPY $h0
%1:_(<2 x s8>) = COPY $h1
%sext0:_(<2 x s16>) = G_SEXT %0
@@ -60,7 +60,7 @@ body: |
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %zext0:_ KnownBits:00000000???????? SignBits:8
; CHECK-NEXT: %sext1:_ KnownBits:???????????????? SignBits:9
- ; CHECK-NEXT: %res:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %res:_ KnownBits:???????????????? SignBits:8
%0:_(<2 x s8>) = COPY $h0
%1:_(<2 x s8>) = COPY $h1
%zext0:_(<2 x s16>) = G_ZEXT %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
index 4a3457a35256d..fae979d38c6ea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
@@ -249,14 +249,12 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
@@ -521,14 +519,12 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
@@ -793,14 +789,12 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
@@ -1065,14 +1059,12 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
diff --git a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
index 295863f18fd41..be79135c8b831 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
@@ -335,8 +335,6 @@ define void @typei1_orig(i64 %a, ptr %p, ptr %q) {
; CHECK-GI-NEXT: cmtst v0.8h, v0.8h, v0.8h
; CHECK-GI-NEXT: mvn v1.16b, v1.16b
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
; CHECK-GI-NEXT: str q0, [x1]
; CHECK-GI-NEXT: ret
%tmp = xor <16 x i1> zeroinitializer, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index e16ea9883a0c4..b9d65fa0314c4 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -969,8 +969,6 @@ define <4 x i32> @v4f64_i32(<4 x double> %a, <4 x double> %b, <4 x i32> %d, <4 x
; CHECK-GI-NEXT: fcmgt v0.2d, v2.2d, v0.2d
; CHECK-GI-NEXT: fcmgt v1.2d, v3.2d, v1.2d
; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
-; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
; CHECK-GI-NEXT: ret
entry:
@@ -1291,8 +1289,6 @@ define <8 x half> @v8f16_half(<8 x half> %a, <8 x half> %b, <8 x half> %d, <8 x
; CHECK-GI-NOFP16-NEXT: fcmgt v4.4s, v5.4s, v4.4s
; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s
; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v4.8h, v0.8h
-; CHECK-GI-NOFP16-NEXT: shl v0.8h, v0.8h, #15
-; CHECK-GI-NOFP16-NEXT: sshr v0.8h, v0.8h, #15
; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v2.16b, v3.16b
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -1341,9 +1337,9 @@ define <16 x half> @v16f16_half(<16 x half> %a, <16 x half> %b, <16 x half> %d,
; CHECK-GI-NOFP16-NEXT: fcvtl v16.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-GI-NOFP16-NEXT: fcvtl v17.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h
; CHECK-GI-NOFP16-NEXT: fcvtl v18.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: fcvtl2 v2.4s, v2.8h
+; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h
; CHECK-GI-NOFP16-NEXT: fcvtl v19.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: fcvtl2 v3.4s, v3.8h
; CHECK-GI-NOFP16-NEXT: fcmgt v16.4s, v18.4s, v16.4s
@@ -1352,12 +1348,12 @@ define <16 x half> @v16f16_half(<16 x half> %a, <16 x half> %b, <16 x half> %d,
; CHECK-GI-NOFP16-NEXT: fcmgt v1.4s, v3.4s, v1.4s
; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v16.8h, v0.8h
; CHECK-GI-NOFP16-NEXT: uzp1 v1.8h, v2.8h, v1.8h
-; CHECK-GI-NOFP16-NEXT: shl v0.8h, v0.8h, #15
-; CHECK-GI-NOFP16-NEXT: shl v1.8h, v1.8h, #15
-; CHECK-GI-NOFP16-NEXT: sshr v0.8h, v0.8h, #15
-; CHECK-GI-NOFP16-NEXT: sshr v1.8h, v1.8h, #15
-; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v4.16b, v6.16b
-; CHECK-GI-NOFP16-NEXT: bsl v1.16b, v5.16b, v7.16b
+; CHECK-GI-NOFP16-NEXT: and v2.16b, v4.16b, v0.16b
+; CHECK-GI-NOFP16-NEXT: bic v0.16b, v6.16b, v0.16b
+; CHECK-GI-NOFP16-NEXT: and v3.16b, v5.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: bic v1.16b, v7.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: orr v0.16b, v2.16b, v0.16b
+; CHECK-GI-NOFP16-NEXT: orr v1.16b, v3.16b, v1.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: v16f16_half:
diff --git a/llvm/test/CodeGen/AArch64/scmp.ll b/llvm/test/CodeGen/AArch64/scmp.ll
index 7a73578f43e80..73cbd2cbeee48 100644
--- a/llvm/test/CodeGen/AArch64/scmp.ll
+++ b/llvm/test/CodeGen/AArch64/scmp.ll
@@ -310,10 +310,6 @@ define <16 x i8> @signOf_neon_scmp(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16>
; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: uzp1 v1.16b, v4.16b, v5.16b
-; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-GI-NEXT: shl v1.16b, v1.16b, #7
-; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
-; CHECK-GI-NEXT: sshr v1.16b, v1.16b, #7
; CHECK-GI-NEXT: sub v0.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/ucmp.ll b/llvm/test/CodeGen/AArch64/ucmp.ll
index ad46e4abc477c..af8225307fedd 100644
--- a/llvm/test/CodeGen/AArch64/ucmp.ll
+++ b/llvm/test/CodeGen/AArch64/ucmp.ll
@@ -348,10 +348,6 @@ define <16 x i8> @signOf_neon(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_
; CHECK-GI-NEXT: cmhi v1.8h, v3.8h, v1.8h
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: uzp1 v1.16b, v4.16b, v5.16b
-; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-GI-NEXT: shl v1.16b, v1.16b, #7
-; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
-; CHECK-GI-NEXT: sshr v1.16b, v1.16b, #7
; CHECK-GI-NEXT: sub v0.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: ret
entry:
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