[llvm] [AMDGPU] Swap select operands to allow later v_cndmask shrinking into vop2 (PR #142354)
Ana Mihajlovic via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 2 03:09:58 PDT 2025
https://github.com/mihajlovicana created https://github.com/llvm/llvm-project/pull/142354
The goal of this is swapping the operands in v_cndmask x, y, where y is a constant, to use the vop2 format instead of vop3. This also requires inverting the comparison (instruction generating the vcc that will be used by v_cndmask). Doing so allows for the later merging of these instructions into v_dual_cndmask.
>From 72a06ddeffc284d258e2fc805349f4424cf169b8 Mon Sep 17 00:00:00 2001
From: Ana Mihajlovic <Ana.Mihajlovic at amd.com>
Date: Mon, 2 Jun 2025 10:41:58 +0200
Subject: [PATCH 1/2] test precommit
---
llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll | 764 +++++++++++++++++++++
1 file changed, 764 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll b/llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll
new file mode 100644
index 0000000000000..12ccdfff07c6f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll
@@ -0,0 +1,764 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GCN
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=GCN
+
+;tests for integer 32
+define amdgpu_cs void @test_i32_sge(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_i32_sge:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp sge i32 %a, 2
+ %val1 = select i1 %vcc, i32 %p, i32 0
+ %val2 = select i1 %vcc, i32 %q, i32 0
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_i32_sle(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_i32_sle:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 3, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp sle i32 %a, 2
+ %val1 = select i1 %vcc, i32 %p, i32 0
+ %val2 = select i1 %vcc, i32 %q, i32 0
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_i32_sgt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_i32_sgt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 2, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp sgt i32 2, %a
+ %val1 = select i1 %vcc, i32 0, i32 %p
+ %val2 = select i1 %vcc, i32 0, i32 %q
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_i32_slt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_i32_slt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 2, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp slt i32 2, %a
+ %val1 = select i1 %vcc, i32 0, i32 %p
+ %val2 = select i1 %vcc, i32 0, i32 %q
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+;tests for integer 64
+define amdgpu_cs void @test_i64_sge(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_i64_sge:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_i64_e32 vcc_lo, 1, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp sge i64 %a, 2
+ %val1 = select i1 %vcc, i64 %p, i64 0
+ %val2 = select i1 %vcc, i64 %q, i64 0
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_i64_sle(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_i64_sle:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_i64_e32 vcc_lo, 3, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp sle i64 %a, 2
+ %val1 = select i1 %vcc, i64 %p, i64 0
+ %val2 = select i1 %vcc, i64 %q, i64 0
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_i64_sgt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_i64_sgt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_i64_e32 vcc_lo, 2, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp sgt i64 2, %a
+ %val1 = select i1 %vcc, i64 0, i64 %p
+ %val2 = select i1 %vcc, i64 0, i64 %q
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_i64_slt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_i64_slt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_i64_e32 vcc_lo, 2, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp slt i64 2, %a
+ %val1 = select i1 %vcc, i64 0, i64 %p
+ %val2 = select i1 %vcc, i64 0, i64 %q
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+;tests for unsigned 32
+define amdgpu_cs void @test_u32_eq(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u32_eq:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp eq i32 1, %a
+ %val1 = select i1 %vcc, i32 0, i32 %p
+ %val2 = select i1 %vcc, i32 0, i32 %q
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_negative_case(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_negative_case:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, -1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp eq i32 %a, -1
+ %val1 = select i1 %vcc, i32 %p, i32 0
+ %val2 = select i1 %vcc, i32 0, i32 %q
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_mixed(i32 %a, i32 %p, i32 %q, i32 %r, i32 %s, ptr addrspace(1) %out) {
+; GCN-LABEL: test_mixed:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, -1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[5:6], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp eq i32 -1, %a
+ %val1 = select i1 %vcc, i32 0, i32 %p
+ %val2 = select i1 %vcc, i32 %q, i32 0
+ %val3 = select i1 %vcc, i32 0, i32 %r
+ %val4 = select i1 %vcc, i32 0, i32 %s
+ %ret0 = insertelement <4 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <4 x i32> %ret0, i32 %val2, i32 1
+ %ret2 = insertelement <4 x i32> %ret1, i32 %val3, i32 2
+ %ret3 = insertelement <4 x i32> %ret2, i32 %val4, i32 3
+ store <4 x i32> %ret3, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_sgpr(i32 %a, i32 %p, i32 inreg %q, i32 inreg %r, ptr addrspace(1) %out) {
+; GCN-LABEL: test_sgpr:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, -1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v5, s0, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v6, s1, 0, vcc_lo
+; GCN-NEXT: global_store_b96 v[2:3], v[4:6], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp eq i32 %a, -1
+ %val1 = select i1 %vcc, i32 %p, i32 0
+ %val2 = select i1 %vcc, i32 0, i32 %q
+ %val3 = select i1 %vcc, i32 0, i32 %r
+ %ret0 = insertelement <3 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <3 x i32> %ret0, i32 %val2, i32 1
+ %ret2 = insertelement <3 x i32> %ret1, i32 %val3, i32 2
+ store <3 x i32> %ret2, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u32_ne(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u32_ne:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 1, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp ne i32 1, %a
+ %val1 = select i1 %vcc, i32 0, i32 %p
+ %val2 = select i1 %vcc, i32 0, i32 %q
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u32_uge(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u32_uge:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 1, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp uge i32 %a, 2
+ %val1 = select i1 %vcc, i32 %p, i32 0
+ %val2 = select i1 %vcc, i32 %q, i32 0
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u32_ule(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u32_ule:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 3, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp ule i32 %a, 2
+ %val1 = select i1 %vcc, i32 %p, i32 0
+ %val2 = select i1 %vcc, i32 %q, i32 0
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u32_ugt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u32_ugt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 2, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp ugt i32 2, %a
+ %val1 = select i1 %vcc, i32 0, i32 %p
+ %val2 = select i1 %vcc, i32 0, i32 %q
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u32_ult(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u32_ult:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 2, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp ult i32 2, %a
+ %val1 = select i1 %vcc, i32 0, i32 %p
+ %val2 = select i1 %vcc, i32 0, i32 %q
+ %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+ %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+ store <2 x i32> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+;tests for unsigned 64
+define amdgpu_cs void @test_u64_eq(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u64_eq:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, 1, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp eq i64 1, %a
+ %val1 = select i1 %vcc, i64 0, i64 %p
+ %val2 = select i1 %vcc, i64 0, i64 %q
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u64_ne(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u64_ne:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_ne_u64_e32 vcc_lo, 1, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp ne i64 1, %a
+ %val1 = select i1 %vcc, i64 0, i64 %p
+ %val2 = select i1 %vcc, i64 0, i64 %q
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u64_uge(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u64_uge:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp uge i64 %a, 2
+ %val1 = select i1 %vcc, i64 %p, i64 0
+ %val2 = select i1 %vcc, i64 %q, i64 0
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u64_ule(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u64_ule:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_u64_e32 vcc_lo, 3, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp ule i64 %a, 2
+ %val1 = select i1 %vcc, i64 %p, i64 0
+ %val2 = select i1 %vcc, i64 %q, i64 0
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u64_ugt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u64_ugt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_u64_e32 vcc_lo, 2, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp ugt i64 2, %a
+ %val1 = select i1 %vcc, i64 0, i64 %p
+ %val2 = select i1 %vcc, i64 0, i64 %q
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_u64_ult(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u64_ult:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_u64_e32 vcc_lo, 2, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = icmp ult i64 2, %a
+ %val1 = select i1 %vcc, i64 0, i64 %p
+ %val2 = select i1 %vcc, i64 0, i64 %q
+ %ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
+ %ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
+ store <2 x i64> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+;tests for float 32
+define amdgpu_cs void @test_f32_oeq(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_oeq:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_eq_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp oeq float %a, 2.0
+ %val1 = select i1 %vcc, float 0.0, float %p
+ %val2 = select i1 %vcc, float 0.0, float %q
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f32_negative_modifiers(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_negative_modifiers:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_eq_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, -v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, -v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %r = fneg float %p
+ %s = fneg float %q
+ %vcc = fcmp oeq float 2.0, %a
+ %val1 = select i1 %vcc, float 0.0, float %r
+ %val2 = select i1 %vcc, float 0.0, float %s
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f32_one(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_one:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lg_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp one float %a, 2.0
+ %val1 = select i1 %vcc, float 0.0, float %p
+ %val2 = select i1 %vcc, float 0.0, float %q
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f32_ord(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_ord:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp ord float %a, 2.0
+ %val1 = select i1 %vcc, float 0.0, float %p
+ %val2 = select i1 %vcc, float 0.0, float %q
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f32_uno(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_uno:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp uno float %a, 2.0
+ %val1 = select i1 %vcc, float 0.0, float %p
+ %val2 = select i1 %vcc, float 0.0, float %q
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f32_oge(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_oge:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp oge float 2.0, %a
+ %val1 = select i1 %vcc, float 0.0, float %p
+ %val2 = select i1 %vcc, float 0.0, float %q
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f32_ole(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_ole:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp ole float 2.0, %a
+ %val1 = select i1 %vcc, float 0.0, float %p
+ %val2 = select i1 %vcc, float 0.0, float %q
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f32_ogt(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_ogt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp ogt float 2.0, %a
+ %val1 = select i1 %vcc, float 0.0, float %p
+ %val2 = select i1 %vcc, float 0.0, float %q
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f32_olt(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_olt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp olt float 2.0, %a
+ %val1 = select i1 %vcc, float 0.0, float %p
+ %val2 = select i1 %vcc, float 0.0, float %q
+ %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+ %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+ store <2 x float> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+;tests for float64
+define amdgpu_cs void @test_f64_oeq(double %a, double %p, double %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64_oeq:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_eq_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp oeq double 2.0, %a
+ %val1 = select i1 %vcc, double 0.0, double %p
+ %val2 = select i1 %vcc, double 0.0, double %q
+ %ret0 = insertelement <2 x double> poison, double %val1, i32 0
+ %ret1 = insertelement <2 x double> %ret0, double %val2, i32 1
+ store <2 x double> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f64_one(double %a, double %p, double %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64_one:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lg_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp one double 2.0, %a
+ %val1 = select i1 %vcc, double 0.0, double %p
+ %val2 = select i1 %vcc, double 0.0, double %q
+ %ret0 = insertelement <2 x double> poison, double %val1, i32 0
+ %ret1 = insertelement <2 x double> %ret0, double %val2, i32 1
+ store <2 x double> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f64_oge(double %a, double %p, double %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64_oge:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_ge_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp oge double 2.0, %a
+ %val1 = select i1 %vcc, double 0.0, double %p
+ %val2 = select i1 %vcc, double 0.0, double %q
+ %ret0 = insertelement <2 x double> poison, double %val1, i32 0
+ %ret1 = insertelement <2 x double> %ret0, double %val2, i32 1
+ store <2 x double> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f64_ole(double %a, double %p, double %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64_ole:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp ole double 2.0, %a
+ %val1 = select i1 %vcc, double 0.0, double %p
+ %val2 = select i1 %vcc, double 0.0, double %q
+ %ret0 = insertelement <2 x double> poison, double %val1, i32 0
+ %ret1 = insertelement <2 x double> %ret0, double %val2, i32 1
+ store <2 x double> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f64_ogt(double %a, double %p, double %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64_ogt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp ogt double 2.0, %a
+ %val1 = select i1 %vcc, double 0.0, double %p
+ %val2 = select i1 %vcc, double 0.0, double %q
+ %ret0 = insertelement <2 x double> poison, double %val1, i32 0
+ %ret1 = insertelement <2 x double> %ret0, double %val2, i32 1
+ store <2 x double> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f64_olt(double %a, double %p, double %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64_olt:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp olt double 2.0, %a
+ %val1 = select i1 %vcc, double 0.0, double %p
+ %val2 = select i1 %vcc, double 0.0, double %q
+ %ret0 = insertelement <2 x double> poison, double %val1, i32 0
+ %ret1 = insertelement <2 x double> %ret0, double %val2, i32 1
+ store <2 x double> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f64_ord(double %a, double %p, double %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64_ord:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp ord double 2.0, %a
+ %val1 = select i1 %vcc, double 0.0, double %p
+ %val2 = select i1 %vcc, double 0.0, double %q
+ %ret0 = insertelement <2 x double> poison, double %val1, i32 0
+ %ret1 = insertelement <2 x double> %ret0, double %val2, i32 1
+ store <2 x double> %ret1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @test_f64_uno(double %a, double %p, double %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64_uno:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
+; GCN-NEXT: s_endpgm
+.entry:
+ %vcc = fcmp uno double 2.0, %a
+ %val1 = select i1 %vcc, double 0.0, double %p
+ %val2 = select i1 %vcc, double 0.0, double %q
+ %ret0 = insertelement <2 x double> poison, double %val1, i32 0
+ %ret1 = insertelement <2 x double> %ret0, double %val2, i32 1
+ store <2 x double> %ret1, ptr addrspace(1) %out
+ ret void
+}
>From 6206f4dfd43863e85c6b9af400ca2831171a69ff Mon Sep 17 00:00:00 2001
From: Ana Mihajlovic <Ana.Mihajlovic at amd.com>
Date: Mon, 2 Jun 2025 12:06:29 +0200
Subject: [PATCH 2/2] [AMDGPU] Swap select operands to allow later v_cndmask
shrinking into vop2
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 30 +-
.../CodeGen/AMDGPU/extract_vector_dynelt.ll | 93 +-
llvm/test/CodeGen/AMDGPU/fmaximum3.ll | 204 +-
llvm/test/CodeGen/AMDGPU/fminimum3.ll | 204 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll | 24 +-
.../CodeGen/AMDGPU/insert_vector_dynelt.ll | 48 +-
llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll | 1656 ++++++++---------
llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll | 1656 ++++++++---------
llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 5 +-
llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll | 188 +-
llvm/test/CodeGen/AMDGPU/uaddsat.ll | 29 +-
llvm/test/CodeGen/AMDGPU/usubsat.ll | 29 +-
llvm/test/CodeGen/AMDGPU/v_cndmask.ll | 30 +-
.../CodeGen/AMDGPU/vector-reduce-fmaximum.ll | 840 ++++-----
.../CodeGen/AMDGPU/vector-reduce-fminimum.ll | 840 ++++-----
15 files changed, 2932 insertions(+), 2944 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 5f41bd7d8a617..1a5d2232213ec 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4710,6 +4710,11 @@ AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
return SDValue();
}
+bool isFnegOrFabs(SDValue &V) {
+ unsigned Opcode = V.getOpcode();
+ return Opcode == ISD::FNEG || Opcode == ISD::FABS;
+}
+
SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
@@ -4727,7 +4732,30 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
SDValue True = N->getOperand(1);
SDValue False = N->getOperand(2);
- if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
+ int ShouldSwap = 0;
+ for (auto it = Cond->use_begin(); it != Cond->use_end(); it++) {
+ auto User = it->getUser();
+
+ if (User->getOpcode() != ISD::SELECT) {
+ ShouldSwap = 0;
+ break;
+ }
+
+ auto Op1 = User->getOperand(1);
+ auto Op2 = User->getOperand(2);
+
+ // if the operand is defined by fneg or fabs it means the instruction
+ // will have source modifiers and therefore can't be shrinked to vop2
+ if (isFnegOrFabs(Op1) || isFnegOrFabs(Op2))
+ continue;
+
+ if (!Op1->isDivergent() && Op2->isDivergent())
+ ShouldSwap++;
+ else if (Op1->isDivergent() && !Op2->isDivergent())
+ ShouldSwap--;
+ }
+
+ if (Cond->hasOneUse() || ShouldSwap > 0) {
SelectionDAG &DAG = DCI.DAG;
if (DAG.isConstantValueOfAnyType(True) &&
!DAG.isConstantValueOfAnyType(False)) {
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index c69b0cce3d208..9ddf3e9340435 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -1097,71 +1097,72 @@ define double @double16_extelt_vec(i32 %sel) {
; GCN-LABEL: double16_extelt_vec:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v3, 0x3ff19999
-; GCN-NEXT: v_mov_b32_e32 v4, 0x4000cccc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 2, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0x9999999a
; GCN-NEXT: v_mov_b32_e32 v2, 0xcccccccd
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: v_mov_b32_e32 v4, 0x4008cccc
-; GCN-NEXT: s_or_b64 vcc, s[4:5], vcc
+; GCN-NEXT: v_mov_b32_e32 v3, 0x3ff19999
+; GCN-NEXT: v_mov_b32_e32 v4, 0x4000cccc
+; GCN-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
+; GCN-NEXT: v_mov_b32_e32 v4, 0x4008cccc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 2, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GCN-NEXT: v_mov_b32_e32 v4, 0x40106666
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 3, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GCN-NEXT: v_mov_b32_e32 v4, 0x40146666
-; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[4:5]
-; GCN-NEXT: s_or_b64 s[4:5], s[4:5], vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 4, v0
+; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5]
+; GCN-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-NEXT: v_mov_b32_e32 v4, 0x40186666
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 5, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GCN-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v5, 0x401c6666
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 6, v0
; GCN-NEXT: v_mov_b32_e32 v4, 0x66666666
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GCN-NEXT: s_or_b64 vcc, vcc, s[4:5]
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GCN-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v4, 0x40203333
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 7, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GCN-NEXT: v_mov_b32_e32 v4, 0x40223333
-; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[4:5]
-; GCN-NEXT: s_or_b64 s[4:5], s[4:5], vcc
+; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 8, v0
+; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5]
+; GCN-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-NEXT: v_mov_b32_e32 v4, 0x40243333
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 9, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 9, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GCN-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v4, 0x40263333
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 10, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 10, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GCN-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v4, 0x40283333
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 11, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 11, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GCN-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v4, 0x402a3333
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 12, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 12, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GCN-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v4, 0x402c3333
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 13, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 13, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GCN-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v5, 0x402e3333
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 14, v0
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 14, v0
; GCN-NEXT: v_mov_b32_e32 v4, 0x33333333
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GCN-NEXT: s_or_b64 vcc, vcc, s[4:5]
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 15, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GCN-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 15, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v1, 0x40301999
-; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
%ext = extractelement <16 x double> <double 1.1, double 2.1, double 3.1, double 4.1, double 5.1, double 6.1, double 7.1, double 8.1, double 9.1, double 10.1, double 11.1, double 12.1, double 13.1, double 14.1, double 15.1, double 16.1>, i32 %sel
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
index 53d940e1e6c1a..8a17a759ac334 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
@@ -3167,15 +3167,15 @@ define double @v_fmaximum3_f64(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.maximum.f64(double %a, double %b)
%max1 = call double @llvm.maximum.f64(double %max0, double %c)
@@ -3200,15 +3200,15 @@ define double @v_fmaximum3_f64_commute(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.maximum.f64(double %a, double %b)
%max1 = call double @llvm.maximum.f64(double %c, double %max0)
@@ -3274,15 +3274,15 @@ define double @v_fmaximum3_f64_fabs0(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], |v[0:1]|, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, |v[0:1]|, v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call double @llvm.fabs.f64(double %a)
%max0 = call double @llvm.maximum.f64(double %a.fabs, double %b)
@@ -3308,15 +3308,15 @@ define double @v_fmaximum3_f64_fabs1(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], |v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[2:3]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], |v[2:3]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%b.fabs = call double @llvm.fabs.f64(double %b)
%max0 = call double @llvm.maximum.f64(double %a, double %b.fabs)
@@ -3342,15 +3342,15 @@ define double @v_fmaximum3_f64_fabs2(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], |v[4:5]|
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[4:5]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], |v[4:5]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%c.fabs = call double @llvm.fabs.f64(double %c)
%max0 = call double @llvm.maximum.f64(double %a, double %b)
@@ -3376,15 +3376,15 @@ define double @v_fmaximum3_f64_fabs_all(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], |v[0:1]|, |v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], |v[4:5]|
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[4:5]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], |v[4:5]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call double @llvm.fabs.f64(double %a)
%b.fabs = call double @llvm.fabs.f64(double %b)
@@ -3412,15 +3412,15 @@ define double @v_fmaximum3_f64_fneg_all(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], -v[0:1], -v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, -v[0:1], -v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], -v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], -v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fneg = fneg double %a
%b.fneg = fneg double %b
@@ -3448,15 +3448,15 @@ define double @v_fmaximum3_f64_fneg_fabs_all(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], -|v[0:1]|, -|v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -|v[0:1]|, -|v[2:3]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, -|v[0:1]|, -|v[2:3]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], -|v[4:5]|
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -|v[4:5]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], -|v[4:5]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call double @llvm.fabs.f64(double %a)
%b.fabs = call double @llvm.fabs.f64(double %b)
@@ -3487,15 +3487,15 @@ define double @v_fmaximum3_f64_fneg0(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], -v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, -v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fneg = fneg double %a
%max0 = call double @llvm.maximum.f64(double %a.fneg, double %b)
@@ -3521,15 +3521,15 @@ define double @v_fmaximum3_f64_fneg1(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], -v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], -v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%b.fneg = fneg double %b
%max0 = call double @llvm.maximum.f64(double %a, double %b.fneg)
@@ -3555,15 +3555,15 @@ define double @v_fmaximum3_f64_fneg2(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], -v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], -v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%c.fneg = fneg double %c
%max0 = call double @llvm.maximum.f64(double %a, double %b)
@@ -3591,15 +3591,15 @@ define double @v_fmaximum3_f64_const0(double %b, double %c) {
; GFX9-NEXT: s_mov_b32 s1, 0x40200000
; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.maximum.f64(double 8.0, double %b)
%max1 = call double @llvm.maximum.f64(double %max0, double %c)
@@ -3624,16 +3624,16 @@ define double @v_fmaximum3_f64__const2(double %a, double %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s1, 0x40200000
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], s[0:1]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.maximum.f64(double %a, double %b)
%max1 = call double @llvm.maximum.f64(double %max0, double 8.0)
@@ -3658,15 +3658,15 @@ define double @v_fmaximum3_f64_inlineimm0(double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], 4.0
; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.maximum.f64(double 4.0, double %b)
%max1 = call double @llvm.maximum.f64(double %max0, double %c)
@@ -3691,15 +3691,15 @@ define double @v_fmaximum3_f64__inlineimm(double %a, double %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], 4.0
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.maximum.f64(double %a, double %b)
%max1 = call double @llvm.maximum.f64(double %max0, double 4.0)
@@ -3726,16 +3726,16 @@ define double @v_fmaximum3_f64_const1_const2(double %a) {
; GFX9-NEXT: s_mov_b32 s1, 0x40200000
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v4, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s1, 0x40300000
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], s[0:1]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.maximum.f64(double %a, double 8.0)
%max1 = call double @llvm.maximum.f64(double %max0, double 16.0)
@@ -4003,15 +4003,15 @@ define <2 x double> @v_no_fmaximum3_f64__multi_use(double %a, double %b, double
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.maximum.f64(double %a, double %b)
%max1 = call double @llvm.maximum.f64(double %max0, double %c)
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum3.ll b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
index d1d0c0dcdb7e0..58d89d4076376 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
@@ -3167,15 +3167,15 @@ define double @v_fminimum3_f64(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.minimum.f64(double %a, double %b)
%max1 = call double @llvm.minimum.f64(double %max0, double %c)
@@ -3200,15 +3200,15 @@ define double @v_fminimum3_f64_commute(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.minimum.f64(double %a, double %b)
%max1 = call double @llvm.minimum.f64(double %c, double %max0)
@@ -3274,15 +3274,15 @@ define double @v_fminimum3_f64_fabs0(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], |v[0:1]|, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, |v[0:1]|, v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call double @llvm.fabs.f64(double %a)
%max0 = call double @llvm.minimum.f64(double %a.fabs, double %b)
@@ -3308,15 +3308,15 @@ define double @v_fminimum3_f64_fabs1(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], |v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[2:3]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], |v[2:3]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%b.fabs = call double @llvm.fabs.f64(double %b)
%max0 = call double @llvm.minimum.f64(double %a, double %b.fabs)
@@ -3342,15 +3342,15 @@ define double @v_fminimum3_f64_fabs2(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], |v[4:5]|
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[4:5]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], |v[4:5]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%c.fabs = call double @llvm.fabs.f64(double %c)
%max0 = call double @llvm.minimum.f64(double %a, double %b)
@@ -3376,15 +3376,15 @@ define double @v_fminimum3_f64_fabs_all(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], |v[0:1]|, |v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], |v[4:5]|
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[4:5]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], |v[4:5]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call double @llvm.fabs.f64(double %a)
%b.fabs = call double @llvm.fabs.f64(double %b)
@@ -3412,15 +3412,15 @@ define double @v_fminimum3_f64_fneg_all(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], -v[0:1], -v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, -v[0:1], -v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], -v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], -v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fneg = fneg double %a
%b.fneg = fneg double %b
@@ -3448,15 +3448,15 @@ define double @v_fminimum3_f64_fneg_fabs_all(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], -|v[0:1]|, -|v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -|v[0:1]|, -|v[2:3]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, -|v[0:1]|, -|v[2:3]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], -|v[4:5]|
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -|v[4:5]|
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], -|v[4:5]|
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call double @llvm.fabs.f64(double %a)
%b.fabs = call double @llvm.fabs.f64(double %b)
@@ -3487,15 +3487,15 @@ define double @v_fminimum3_f64_fneg0(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], -v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, -v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.fneg = fneg double %a
%max0 = call double @llvm.minimum.f64(double %a.fneg, double %b)
@@ -3521,15 +3521,15 @@ define double @v_fminimum3_f64_fneg1(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], -v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], -v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%b.fneg = fneg double %b
%max0 = call double @llvm.minimum.f64(double %a, double %b.fneg)
@@ -3555,15 +3555,15 @@ define double @v_fminimum3_f64_fneg2(double %a, double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], -v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e64 vcc, v[0:1], -v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%c.fneg = fneg double %c
%max0 = call double @llvm.minimum.f64(double %a, double %b)
@@ -3591,15 +3591,15 @@ define double @v_fminimum3_f64_const0(double %b, double %c) {
; GFX9-NEXT: s_mov_b32 s1, 0x40200000
; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.minimum.f64(double 8.0, double %b)
%max1 = call double @llvm.minimum.f64(double %max0, double %c)
@@ -3624,16 +3624,16 @@ define double @v_fminimum3_f64__const2(double %a, double %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s1, 0x40200000
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], s[0:1]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.minimum.f64(double %a, double %b)
%max1 = call double @llvm.minimum.f64(double %max0, double 8.0)
@@ -3658,15 +3658,15 @@ define double @v_fminimum3_f64_inlineimm0(double %b, double %c) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], 4.0
; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.minimum.f64(double 4.0, double %b)
%max1 = call double @llvm.minimum.f64(double %max0, double %c)
@@ -3691,15 +3691,15 @@ define double @v_fminimum3_f64__inlineimm(double %a, double %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], 4.0
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.minimum.f64(double %a, double %b)
%max1 = call double @llvm.minimum.f64(double %max0, double 4.0)
@@ -3726,16 +3726,16 @@ define double @v_fminimum3_f64_const1_const2(double %a) {
; GFX9-NEXT: s_mov_b32 s1, 0x40200000
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v4, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s1, 0x40300000
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], s[0:1]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.minimum.f64(double %a, double 8.0)
%max1 = call double @llvm.minimum.f64(double %max0, double 16.0)
@@ -4003,15 +4003,15 @@ define <2 x double> @v_no_fminimum3_f64__multi_use(double %a, double %b, double
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%max0 = call double @llvm.minimum.f64(double %a, double %b)
%max1 = call double @llvm.minimum.f64(double %max0, double %c)
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 46da9d33639b6..feed8c4d6b745 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -1624,20 +1624,20 @@ define double @v_fneg_inv2pi_minimum_f64(double %a) #0 {
; SI-NEXT: s_mov_b32 s4, 0x6dc9c882
; SI-NEXT: s_mov_b32 s5, 0xbfc45f30
; SI-NEXT: v_max_f64 v[2:3], -v[0:1], s[4:5]
-; SI-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]
+; SI-NEXT: v_cmp_o_f64_e64 vcc, -v[0:1], -v[0:1]
; SI-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; SI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_fneg_inv2pi_minimum_f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_min_f64 v[2:3], v[0:1], 0.15915494309189532
-; VI-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
+; VI-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, 0xfff80000
-; VI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; VI-NEXT: v_cndmask_b32_e64 v1, -v3, v1, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-NEXT: v_cndmask_b32_e64 v1, v1, -v3, vcc
; VI-NEXT: s_setpc_b64 s[30:31]
%min = call double @llvm.minimum.f64(double 0x3fc45f306dc9c882, double %a)
%fneg = fneg double %min
@@ -1651,20 +1651,20 @@ define double @v_fneg_neg_inv2pi_minimum_f64(double %a) #0 {
; SI-NEXT: s_mov_b32 s4, 0x6dc9c882
; SI-NEXT: s_mov_b32 s5, 0x3fc45f30
; SI-NEXT: v_max_f64 v[2:3], -v[0:1], s[4:5]
-; SI-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]
+; SI-NEXT: v_cmp_o_f64_e64 vcc, -v[0:1], -v[0:1]
; SI-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; SI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_fneg_neg_inv2pi_minimum_f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_max_f64 v[2:3], -v[0:1], 0.15915494309189532
-; VI-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]
+; VI-NEXT: v_cmp_o_f64_e64 vcc, -v[0:1], -v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; VI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; VI-NEXT: s_setpc_b64 s[30:31]
%min = call double @llvm.minimum.f64(double 0xbfc45f306dc9c882, double %a)
%fneg = fneg double %min
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
index 6925a98f643b9..2e037335ce37a 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
@@ -1919,31 +1919,31 @@ define <8 x double> @double8_inselt_vec(<8 x double> %vec, i32 %sel) {
; GCN-LABEL: double8_inselt_vec:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_mov_b32_e32 v17, 0x3ff00000
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16
-; GCN-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16
-; GCN-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16
-; GCN-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16
-; GCN-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16
-; GCN-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16
-; GCN-NEXT: v_cndmask_b32_e64 v14, v14, 0, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 1, v16
+; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 2, v16
+; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 3, v16
+; GCN-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 4, v16
+; GCN-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 5, v16
+; GCN-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 6, v16
+; GCN-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 7, v16
+; GCN-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
%v = insertelement <8 x double> %vec, double 1.000000e+00, i32 %sel
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
index a18e5ace18704..f0d7ed46a6082 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
@@ -13,60 +13,60 @@ define double @v_maximum_f64(double %src0, double %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f64:
@@ -131,60 +131,60 @@ define double @v_maximum_f64__nsz(double %src0, double %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f64__nsz:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_f64__nsz:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_f64__nsz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f64__nsz:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f64__nsz:
@@ -250,10 +250,10 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f64__nnan_src0:
@@ -261,10 +261,10 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_f64__nnan_src0:
@@ -272,10 +272,10 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX900-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_f64__nnan_src0:
@@ -283,11 +283,11 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) {
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX950-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f64__nnan_src0:
@@ -295,9 +295,9 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f64__nnan_src0:
@@ -306,10 +306,10 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) {
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f64__nnan_src0:
@@ -334,10 +334,10 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f64__nnan_src1:
@@ -345,10 +345,10 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_f64__nnan_src1:
@@ -356,10 +356,10 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX900-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_f64__nnan_src1:
@@ -367,11 +367,11 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) {
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX950-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f64__nnan_src1:
@@ -379,9 +379,9 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f64__nnan_src1:
@@ -390,10 +390,10 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) {
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f64__nnan_src1:
@@ -520,85 +520,85 @@ define <2 x double> @v_maximum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX7-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v2f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX8-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v2f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX900-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX900-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v2f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX950-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX950-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[6:7]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v8, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v2f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v5, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v2f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v5, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v2f64:
@@ -670,85 +670,85 @@ define <2 x double> @v_maximum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX7-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v2f64__nsz:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX8-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v2f64__nsz:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX900-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX900-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v2f64__nsz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX950-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX950-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[6:7]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v8, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v2f64__nsz:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v5, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v2f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v5, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v2f64__nsz:
@@ -955,109 +955,109 @@ define <3 x double> @v_maximum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX7-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX7-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX7-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v3f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX8-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX8-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v3f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX900-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX900-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX900-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v3f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX950-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
; GFX950-NEXT: v_mov_b32_e32 v12, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v13, v12, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v12, v13, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[8:9]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v7, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v7, vcc
; GFX950-NEXT: v_max_f64 v[6:7], v[4:5], v[10:11]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[10:11]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v12, v7, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v3f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX10-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[8:9]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[8:9]
; GFX10-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s5
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v7, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v9, s5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v3f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[8:9]
; GFX11-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s1
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v13, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v7, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v8, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v9, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v3f64:
@@ -1136,109 +1136,109 @@ define <3 x double> @v_maximum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX7-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX7-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX7-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v3f64__nsz:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX8-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX8-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v3f64__nsz:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX900-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX900-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX900-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v3f64__nsz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX950-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
; GFX950-NEXT: v_mov_b32_e32 v12, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v13, v12, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v12, v13, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[8:9]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v7, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v7, vcc
; GFX950-NEXT: v_max_f64 v[6:7], v[4:5], v[10:11]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[10:11]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v12, v7, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v3f64__nsz:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX10-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[8:9]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[8:9]
; GFX10-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s5
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v7, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v9, s5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v3f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[12:13], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[8:9]
; GFX11-NEXT: v_max_f64 v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s1
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v13, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v7, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v8, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v9, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v3f64__nsz:
@@ -1317,134 +1317,134 @@ define <4 x double> @v_maximum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX7-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX7-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX7-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX7-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v4f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX8-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX8-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX8-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX8-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v4f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX900-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX900-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX900-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX900-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v4f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX950-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX950-NEXT: v_mov_b32_e32 v16, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[10:11]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[10:11]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v16, v9, vcc
; GFX950-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[12:13]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v16, v9, vcc
; GFX950-NEXT: v_max_f64 v[8:9], v[6:7], v[14:15]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[6:7], v[14:15]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v16, v9, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v4f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX10-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[10:11]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[10:11]
; GFX10-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[12:13]
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[12:13]
; GFX10-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cmp_o_f64_e64 s6, v[6:7], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v10, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v11, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v12, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v13, s6
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX11-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[10:11]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[10:11]
; GFX11-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[12:13]
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[12:13]
; GFX11-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cmp_o_f64_e64 s2, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v8, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v9, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v10, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v11, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v12, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v13, s2
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v4f64:
@@ -1530,134 +1530,134 @@ define <4 x double> @v_maximum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX7-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX7-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX7-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX7-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v4f64__nsz:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX8-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX8-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX8-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX8-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v4f64__nsz:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX900-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX900-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX900-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX900-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v4f64__nsz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX950-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX950-NEXT: v_mov_b32_e32 v16, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[10:11]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[10:11]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v16, v9, vcc
; GFX950-NEXT: v_max_f64 v[8:9], v[4:5], v[12:13]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[12:13]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v16, v9, vcc
; GFX950-NEXT: v_max_f64 v[8:9], v[6:7], v[14:15]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[6:7], v[14:15]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v16, v9, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v4f64__nsz:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX10-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[10:11]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[10:11]
; GFX10-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[12:13]
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[12:13]
; GFX10-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cmp_o_f64_e64 s6, v[6:7], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v10, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v11, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v12, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v13, s6
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v4f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX11-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[10:11]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[10:11]
; GFX11-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[12:13]
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[12:13]
; GFX11-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cmp_o_f64_e64 s2, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v8, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v9, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v10, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v11, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v12, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v13, s2
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v4f64__nsz:
@@ -1744,39 +1744,39 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX7-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[18:19]
; GFX7-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX7-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX7-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX7-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[24:25]
; GFX7-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[26:27]
; GFX7-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[28:29]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v34, v33, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v16, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v34, v17, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v18, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v34, v19, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, v20, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v34, v21, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, v22, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v34, v23, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, v24, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v34, v25, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v12, 0, v26, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v13, v34, v27, s[14:15]
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_max_f64 v[16:17], v[14:15], v[30:31]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
-; GFX7-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[30:31]
+; GFX7-NEXT: v_cndmask_b32_e32 v14, 0, v16, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v15, v34, v17, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v8f64:
@@ -1784,39 +1784,39 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX8-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[18:19]
; GFX8-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX8-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX8-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX8-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[24:25]
; GFX8-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[26:27]
; GFX8-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[28:29]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v34, v33, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v16, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v34, v17, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v18, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v34, v19, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v20, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v34, v21, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v22, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v34, v23, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v24, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v34, v25, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, v26, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v34, v27, s[14:15]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[16:17], v[14:15], v[30:31]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
-; GFX8-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[30:31]
+; GFX8-NEXT: v_cndmask_b32_e32 v14, 0, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v34, v17, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v8f64:
@@ -1824,39 +1824,39 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX900-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX900-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[18:19]
; GFX900-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX900-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX900-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX900-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[24:25]
; GFX900-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[26:27]
; GFX900-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX900-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[28:29]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v34, v33, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v16, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v34, v17, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v18, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v34, v19, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, 0, v20, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v34, v21, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v8, 0, v22, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v9, v34, v23, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v10, 0, v24, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v11, v34, v25, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v12, 0, v26, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v13, v34, v27, s[14:15]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_max_f64 v[16:17], v[14:15], v[30:31]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
-; GFX900-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[30:31]
+; GFX900-NEXT: v_cndmask_b32_e32 v14, 0, v16, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v15, v34, v17, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v8f64:
@@ -1865,42 +1865,42 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX950-NEXT: scratch_load_dword v31, off, s32
; GFX950-NEXT: v_mov_b32_e32 v54, 0x7ff80000
; GFX950-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX950-NEXT: v_max_f64 v[34:35], v[2:3], v[18:19]
; GFX950-NEXT: v_max_f64 v[36:37], v[4:5], v[20:21]
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v33, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[18:19]
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v54, v33, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[18:19]
; GFX950-NEXT: v_max_f64 v[38:39], v[6:7], v[22:23]
; GFX950-NEXT: v_max_f64 v[48:49], v[8:9], v[24:25]
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v34, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v35, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[20:21]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v34, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v54, v35, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[20:21]
; GFX950-NEXT: v_max_f64 v[50:51], v[10:11], v[26:27]
; GFX950-NEXT: v_max_f64 v[52:53], v[12:13], v[28:29]
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v36, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v37, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[22:23]
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v36, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v54, v37, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[6:7], v[22:23]
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_max_f64 v[16:17], v[14:15], v[30:31]
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v38, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v7, v39, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v38, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v54, v39, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[8:9], v[24:25]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v8, v48, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v9, v49, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX950-NEXT: v_cndmask_b32_e32 v8, 0, v48, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v9, v54, v49, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[10:11], v[26:27]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v10, v50, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v11, v51, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v50, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v11, v54, v51, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[12:13], v[28:29]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v12, v52, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v13, v53, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
+; GFX950-NEXT: v_cndmask_b32_e32 v12, 0, v52, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v13, v54, v53, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[30:31]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v15, v17, v54, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v14, 0, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v15, v54, v17, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v8f64:
@@ -1908,38 +1908,38 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[16:17]
; GFX10-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[18:19]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[18:19]
; GFX10-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[20:21]
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[20:21]
; GFX10-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[22:23]
+; GFX10-NEXT: v_cmp_o_f64_e64 s6, v[6:7], v[22:23]
; GFX10-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX10-NEXT: v_cmp_u_f64_e64 s7, v[8:9], v[24:25]
+; GFX10-NEXT: v_cmp_o_f64_e64 s7, v[8:9], v[24:25]
; GFX10-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX10-NEXT: v_cmp_u_f64_e64 s8, v[10:11], v[26:27]
+; GFX10-NEXT: v_cmp_o_f64_e64 s8, v[10:11], v[26:27]
; GFX10-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX10-NEXT: v_cmp_u_f64_e64 s9, v[12:13], v[28:29]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v33, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v16, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v17, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v19, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v20, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v21, 0x7ff80000, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v22, 0, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v23, 0x7ff80000, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v24, 0, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v25, 0x7ff80000, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v26, 0, s9
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v27, 0x7ff80000, s9
+; GFX10-NEXT: v_cmp_o_f64_e64 s9, v[12:13], v[28:29]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v33, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v16, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v17, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v18, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v19, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v20, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v21, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v22, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0x7ff80000, v23, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v24, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0x7ff80000, v25, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, v26, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v13, 0x7ff80000, v27, s9
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_max_f64 v[28:29], v[14:15], v[30:31]
-; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[30:31]
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v28, 0, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v29, 0x7ff80000, s10
+; GFX10-NEXT: v_cmp_o_f64_e64 s10, v[14:15], v[30:31]
+; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, v28, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v15, 0x7ff80000, v29, s10
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v8f64:
@@ -1947,39 +1947,39 @@ define <8 x double> @v_maximum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_max_f64 v[32:33], v[0:1], v[16:17]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[16:17]
; GFX11-NEXT: v_max_f64 v[16:17], v[2:3], v[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[18:19]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[18:19]
; GFX11-NEXT: v_max_f64 v[18:19], v[4:5], v[20:21]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[20:21]
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[20:21]
; GFX11-NEXT: v_max_f64 v[20:21], v[6:7], v[22:23]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[22:23]
+; GFX11-NEXT: v_cmp_o_f64_e64 s2, v[6:7], v[22:23]
; GFX11-NEXT: v_max_f64 v[22:23], v[8:9], v[24:25]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[8:9], v[24:25]
+; GFX11-NEXT: v_cmp_o_f64_e64 s3, v[8:9], v[24:25]
; GFX11-NEXT: v_max_f64 v[24:25], v[10:11], v[26:27]
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[10:11], v[26:27]
+; GFX11-NEXT: v_cmp_o_f64_e64 s4, v[10:11], v[26:27]
; GFX11-NEXT: v_max_f64 v[26:27], v[12:13], v[28:29]
-; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[28:29]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v33, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v16, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v17, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v18, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v19, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v20, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v21, 0x7ff80000, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v22, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v23, 0x7ff80000, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v24, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v25, 0x7ff80000, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v26, 0, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v27, 0x7ff80000, s5
+; GFX11-NEXT: v_cmp_o_f64_e64 s5, v[12:13], v[28:29]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v33, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v16, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v17, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v18, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v19, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v20, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v21, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v22, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0x7ff80000, v23, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v24, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v11, 0x7ff80000, v25, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, v26, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v13, 0x7ff80000, v27, s5
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f64 v[28:29], v[14:15], v[30:31]
-; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[30:31]
+; GFX11-NEXT: v_cmp_o_f64_e64 s6, v[14:15], v[30:31]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v28, 0, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v29, 0x7ff80000, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v14, 0, v28, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v15, 0x7ff80000, v29, s6
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v8f64:
@@ -2011,117 +2011,117 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[31:32]
; GFX7-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[31:32]
; GFX7-NEXT: v_max_f64 v[2:3], v[2:3], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[31:32]
; GFX7-NEXT: v_max_f64 v[4:5], v[4:5], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[31:32]
; GFX7-NEXT: v_max_f64 v[6:7], v[6:7], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[31:32]
; GFX7-NEXT: v_max_f64 v[8:9], v[8:9], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[10:11]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[31:32]
; GFX7-NEXT: v_max_f64 v[10:11], v[10:11], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[12:13]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[31:32]
; GFX7-NEXT: v_max_f64 v[12:13], v[12:13], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX7-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[14:15]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[16:17], v[14:15], v[31:32]
; GFX7-NEXT: v_max_f64 v[14:15], v[14:15], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX7-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX7-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[16:17]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[18:19], v[16:17], v[31:32]
; GFX7-NEXT: v_max_f64 v[16:17], v[16:17], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX7-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX7-NEXT: v_cndmask_b32_e64 v16, 0, v16, s[18:19]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[20:21], v[18:19], v[31:32]
; GFX7-NEXT: v_max_f64 v[18:19], v[18:19], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX7-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX7-NEXT: v_cndmask_b32_e64 v18, 0, v18, s[20:21]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[22:23], v[20:21], v[31:32]
; GFX7-NEXT: v_max_f64 v[20:21], v[20:21], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX7-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v20, 0, v20, s[22:23]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[24:25], v[22:23], v[31:32]
; GFX7-NEXT: v_max_f64 v[22:23], v[22:23], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX7-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, v22, s[24:25]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[26:27], v[24:25], v[31:32]
; GFX7-NEXT: v_max_f64 v[24:25], v[24:25], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX7-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, v24, s[26:27]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[28:29], v[26:27], v[31:32]
; GFX7-NEXT: v_max_f64 v[26:27], v[26:27], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX7-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX7-NEXT: v_cndmask_b32_e64 v26, 0, v26, s[28:29]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[40:41], v[28:29], v[31:32]
; GFX7-NEXT: v_max_f64 v[28:29], v[28:29], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX7-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e64 v28, 0, v28, s[40:41]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX7-NEXT: v_max_f64 v[30:31], v[30:31], v[32:33]
; GFX7-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX7-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX7-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX7-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX7-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX7-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX7-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX7-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
-; GFX7-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
-; GFX7-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v32, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v32, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v32, v7, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v32, v9, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v32, v11, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v13, v32, v13, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v15, v32, v15, s[16:17]
+; GFX7-NEXT: v_cndmask_b32_e64 v17, v32, v17, s[18:19]
+; GFX7-NEXT: v_cndmask_b32_e64 v19, v32, v19, s[20:21]
+; GFX7-NEXT: v_cndmask_b32_e64 v21, v32, v21, s[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v23, v32, v23, s[24:25]
+; GFX7-NEXT: v_cndmask_b32_e64 v25, v32, v25, s[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v27, v32, v27, s[28:29]
+; GFX7-NEXT: v_cndmask_b32_e64 v29, v32, v29, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e64 v31, v32, v31, s[42:43]
+; GFX7-NEXT: v_cndmask_b32_e64 v30, 0, v30, s[42:43]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v16f64:
@@ -2130,117 +2130,117 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[31:32]
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[31:32]
; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[31:32]
; GFX8-NEXT: v_max_f64 v[4:5], v[4:5], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[31:32]
; GFX8-NEXT: v_max_f64 v[6:7], v[6:7], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[31:32]
; GFX8-NEXT: v_max_f64 v[8:9], v[8:9], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[10:11]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[31:32]
; GFX8-NEXT: v_max_f64 v[10:11], v[10:11], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[12:13]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[31:32]
; GFX8-NEXT: v_max_f64 v[12:13], v[12:13], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[14:15]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[16:17], v[14:15], v[31:32]
; GFX8-NEXT: v_max_f64 v[14:15], v[14:15], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[16:17]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[18:19], v[16:17], v[31:32]
; GFX8-NEXT: v_max_f64 v[16:17], v[16:17], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v16, 0, v16, s[18:19]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[20:21], v[18:19], v[31:32]
; GFX8-NEXT: v_max_f64 v[18:19], v[18:19], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v18, 0, v18, s[20:21]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[22:23], v[20:21], v[31:32]
; GFX8-NEXT: v_max_f64 v[20:21], v[20:21], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v20, 0, v20, s[22:23]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[24:25], v[22:23], v[31:32]
; GFX8-NEXT: v_max_f64 v[22:23], v[22:23], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, v22, s[24:25]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[26:27], v[24:25], v[31:32]
; GFX8-NEXT: v_max_f64 v[24:25], v[24:25], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, v24, s[26:27]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[28:29], v[26:27], v[31:32]
; GFX8-NEXT: v_max_f64 v[26:27], v[26:27], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v26, 0, v26, s[28:29]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[40:41], v[28:29], v[31:32]
; GFX8-NEXT: v_max_f64 v[28:29], v[28:29], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX8-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e64 v28, 0, v28, s[40:41]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX8-NEXT: v_max_f64 v[30:31], v[30:31], v[32:33]
; GFX8-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX8-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX8-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX8-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX8-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX8-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
-; GFX8-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
-; GFX8-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v32, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v32, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v32, v7, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v32, v9, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v32, v11, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v32, v13, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v15, v32, v15, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v17, v32, v17, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v19, v32, v19, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v21, v32, v21, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v23, v32, v23, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v25, v32, v25, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v27, v32, v27, s[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v29, v32, v29, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e64 v31, v32, v31, s[42:43]
+; GFX8-NEXT: v_cndmask_b32_e64 v30, 0, v30, s[42:43]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_maximum_v16f64:
@@ -2249,117 +2249,117 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[31:32]
; GFX900-NEXT: v_max_f64 v[0:1], v[0:1], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[31:32]
; GFX900-NEXT: v_max_f64 v[2:3], v[2:3], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[31:32]
; GFX900-NEXT: v_max_f64 v[4:5], v[4:5], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[31:32]
; GFX900-NEXT: v_max_f64 v[6:7], v[6:7], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[31:32]
; GFX900-NEXT: v_max_f64 v[8:9], v[8:9], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX900-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[10:11]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[31:32]
; GFX900-NEXT: v_max_f64 v[10:11], v[10:11], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX900-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[12:13]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[31:32]
; GFX900-NEXT: v_max_f64 v[12:13], v[12:13], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX900-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[14:15]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[16:17], v[14:15], v[31:32]
; GFX900-NEXT: v_max_f64 v[14:15], v[14:15], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX900-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX900-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[18:19], v[16:17], v[31:32]
; GFX900-NEXT: v_max_f64 v[16:17], v[16:17], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX900-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX900-NEXT: v_cndmask_b32_e64 v16, 0, v16, s[18:19]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[20:21], v[18:19], v[31:32]
; GFX900-NEXT: v_max_f64 v[18:19], v[18:19], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX900-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX900-NEXT: v_cndmask_b32_e64 v18, 0, v18, s[20:21]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[22:23], v[20:21], v[31:32]
; GFX900-NEXT: v_max_f64 v[20:21], v[20:21], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX900-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX900-NEXT: v_cndmask_b32_e64 v20, 0, v20, s[22:23]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[24:25], v[22:23], v[31:32]
; GFX900-NEXT: v_max_f64 v[22:23], v[22:23], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX900-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX900-NEXT: v_cndmask_b32_e64 v22, 0, v22, s[24:25]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[26:27], v[24:25], v[31:32]
; GFX900-NEXT: v_max_f64 v[24:25], v[24:25], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX900-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v24, 0, v24, s[26:27]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[28:29], v[26:27], v[31:32]
; GFX900-NEXT: v_max_f64 v[26:27], v[26:27], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX900-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX900-NEXT: v_cndmask_b32_e64 v26, 0, v26, s[28:29]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[40:41], v[28:29], v[31:32]
; GFX900-NEXT: v_max_f64 v[28:29], v[28:29], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX900-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX900-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e64 v28, 0, v28, s[40:41]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX900-NEXT: v_max_f64 v[30:31], v[30:31], v[32:33]
; GFX900-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX900-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX900-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX900-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX900-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX900-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX900-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX900-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX900-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
-; GFX900-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
-; GFX900-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v32, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v32, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v32, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v32, v7, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v9, v32, v9, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v11, v32, v11, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v13, v32, v13, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v15, v32, v15, s[16:17]
+; GFX900-NEXT: v_cndmask_b32_e64 v17, v32, v17, s[18:19]
+; GFX900-NEXT: v_cndmask_b32_e64 v19, v32, v19, s[20:21]
+; GFX900-NEXT: v_cndmask_b32_e64 v21, v32, v21, s[22:23]
+; GFX900-NEXT: v_cndmask_b32_e64 v23, v32, v23, s[24:25]
+; GFX900-NEXT: v_cndmask_b32_e64 v25, v32, v25, s[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v27, v32, v27, s[28:29]
+; GFX900-NEXT: v_cndmask_b32_e64 v29, v32, v29, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e64 v31, v32, v31, s[42:43]
+; GFX900-NEXT: v_cndmask_b32_e64 v30, 0, v30, s[42:43]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_maximum_v16f64:
@@ -2410,107 +2410,107 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_max_f64 v[58:59], v[0:1], v[32:33]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[32:33]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[32:33]
; GFX950-NEXT: scratch_load_dword v33, off, s32 offset:112
; GFX950-NEXT: scratch_load_dword v32, off, s32 offset:108
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_max_f64 v[60:61], v[2:3], v[36:37]
-; GFX950-NEXT: v_cmp_u_f64_e64 s[0:1], v[2:3], v[36:37]
+; GFX950-NEXT: v_cmp_o_f64_e64 s[0:1], v[2:3], v[36:37]
; GFX950-NEXT: scratch_load_dword v37, off, s32 offset:120
; GFX950-NEXT: scratch_load_dword v36, off, s32 offset:116
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_max_f64 v[62:63], v[4:5], v[38:39]
-; GFX950-NEXT: v_cmp_u_f64_e64 s[2:3], v[4:5], v[38:39]
+; GFX950-NEXT: v_cmp_o_f64_e64 s[2:3], v[4:5], v[38:39]
; GFX950-NEXT: scratch_load_dword v39, off, s32 offset:128
; GFX950-NEXT: scratch_load_dword v38, off, s32 offset:124
; GFX950-NEXT: v_mov_b32_e32 v2, 0x7ff80000
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_max_f64 v[0:1], v[6:7], v[56:57]
-; GFX950-NEXT: v_cmp_u_f64_e64 s[4:5], v[6:7], v[56:57]
+; GFX950-NEXT: v_cmp_o_f64_e64 s[4:5], v[6:7], v[56:57]
; GFX950-NEXT: s_waitcnt vmcnt(23)
; GFX950-NEXT: v_max_f64 v[56:57], v[8:9], v[46:47]
-; GFX950-NEXT: v_cndmask_b32_e64 v58, v58, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v59, v59, v2, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[46:47]
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
-; GFX950-NEXT: v_cndmask_b32_e64 v7, v1, v2, s[4:5]
-; GFX950-NEXT: v_cndmask_b32_e64 v8, v56, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v9, v57, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v58, 0, v58, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v59, v2, v59, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[8:9], v[46:47]
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, v0, s[4:5]
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v2, v1, s[4:5]
+; GFX950-NEXT: v_cndmask_b32_e32 v8, 0, v56, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v9, v2, v57, vcc
; GFX950-NEXT: s_waitcnt vmcnt(21)
; GFX950-NEXT: v_max_f64 v[0:1], v[10:11], v[44:45]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[44:45]
-; GFX950-NEXT: v_cndmask_b32_e64 v60, v60, 0, s[0:1]
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v61, v2, s[0:1]
-; GFX950-NEXT: v_cndmask_b32_e64 v10, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v11, v1, v2, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[10:11], v[44:45]
+; GFX950-NEXT: v_cndmask_b32_e64 v60, 0, v60, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v2, v61, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v11, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(19)
; GFX950-NEXT: v_max_f64 v[0:1], v[12:13], v[42:43]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[42:43]
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v62, 0, s[2:3]
-; GFX950-NEXT: v_cndmask_b32_e64 v5, v63, v2, s[2:3]
-; GFX950-NEXT: v_cndmask_b32_e64 v12, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v13, v1, v2, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[12:13], v[42:43]
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, v62, s[2:3]
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v2, v63, s[2:3]
+; GFX950-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v13, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(17)
; GFX950-NEXT: v_max_f64 v[0:1], v[14:15], v[40:41]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[40:41]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[40:41]
; GFX950-NEXT: v_accvgpr_read_b32 v63, a15 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v62, a14 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v14, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v15, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v14, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v15, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(15)
; GFX950-NEXT: v_max_f64 v[0:1], v[16:17], v[54:55]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[16:17], v[54:55]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[16:17], v[54:55]
; GFX950-NEXT: v_accvgpr_read_b32 v61, a13 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v57, a9 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v16, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v17, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v16, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v17, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(13)
; GFX950-NEXT: v_max_f64 v[0:1], v[18:19], v[52:53]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[18:19], v[52:53]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[18:19], v[52:53]
; GFX950-NEXT: v_accvgpr_read_b32 v56, a8 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v47, a7 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v18, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v19, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v18, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v19, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(11)
; GFX950-NEXT: v_max_f64 v[0:1], v[20:21], v[50:51]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[20:21], v[50:51]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[20:21], v[50:51]
; GFX950-NEXT: v_accvgpr_read_b32 v46, a6 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v45, a5 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v20, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v21, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v20, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v21, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(9)
; GFX950-NEXT: v_max_f64 v[0:1], v[22:23], v[48:49]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[22:23], v[48:49]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[22:23], v[48:49]
; GFX950-NEXT: v_accvgpr_read_b32 v44, a4 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v43, a3 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v22, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v23, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v22, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v23, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(6)
; GFX950-NEXT: v_max_f64 v[0:1], v[24:25], v[34:35]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[24:25], v[34:35]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[24:25], v[34:35]
; GFX950-NEXT: v_accvgpr_read_b32 v42, a2 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v24, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v25, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v24, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v25, v2, v1, vcc
; GFX950-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse
; GFX950-NEXT: s_waitcnt vmcnt(4)
; GFX950-NEXT: v_max_f64 v[0:1], v[26:27], v[32:33]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[26:27], v[32:33]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[26:27], v[32:33]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v26, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v27, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v26, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v27, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(2)
; GFX950-NEXT: v_max_f64 v[0:1], v[28:29], v[36:37]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[28:29], v[36:37]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[28:29], v[36:37]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v28, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v29, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v28, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v29, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_max_f64 v[0:1], v[30:31], v[38:39]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[30:31], v[38:39]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[30:31], v[38:39]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v30, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v31, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v30, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v31, v2, v1, vcc
; GFX950-NEXT: v_mov_b32_e32 v0, v58
; GFX950-NEXT: v_mov_b32_e32 v1, v59
; GFX950-NEXT: v_mov_b32_e32 v2, v60
@@ -2551,10 +2551,10 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:104
; GFX10-NEXT: s_waitcnt vmcnt(24)
; GFX10-NEXT: v_max_f64 v[82:83], v[0:1], v[31:32]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[31:32]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[31:32]
; GFX10-NEXT: s_waitcnt vmcnt(22)
; GFX10-NEXT: v_max_f64 v[84:85], v[2:3], v[33:34]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[33:34]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[33:34]
; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120
; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
@@ -2562,81 +2562,81 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108
; GFX10-NEXT: s_waitcnt vmcnt(24)
; GFX10-NEXT: v_max_f64 v[32:33], v[4:5], v[35:36]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[35:36]
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[35:36]
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128
; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
; GFX10-NEXT: s_waitcnt vmcnt(24)
; GFX10-NEXT: v_max_f64 v[34:35], v[6:7], v[48:49]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[48:49]
+; GFX10-NEXT: v_cmp_o_f64_e64 s6, v[6:7], v[48:49]
; GFX10-NEXT: s_waitcnt vmcnt(21)
-; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[52:53]
+; GFX10-NEXT: v_cmp_o_f64_e64 s10, v[14:15], v[52:53]
; GFX10-NEXT: s_waitcnt vmcnt(19)
-; GFX10-NEXT: v_cmp_u_f64_e64 s9, v[12:13], v[54:55]
+; GFX10-NEXT: v_cmp_o_f64_e64 s9, v[12:13], v[54:55]
; GFX10-NEXT: s_waitcnt vmcnt(17)
-; GFX10-NEXT: v_cmp_u_f64_e64 s8, v[10:11], v[64:65]
+; GFX10-NEXT: v_cmp_o_f64_e64 s8, v[10:11], v[64:65]
; GFX10-NEXT: s_waitcnt vmcnt(16)
; GFX10-NEXT: v_max_f64 v[48:49], v[8:9], v[37:38]
-; GFX10-NEXT: v_cmp_u_f64_e64 s7, v[8:9], v[37:38]
+; GFX10-NEXT: v_cmp_o_f64_e64 s7, v[8:9], v[37:38]
; GFX10-NEXT: v_max_f64 v[36:37], v[10:11], v[64:65]
; GFX10-NEXT: v_max_f64 v[38:39], v[12:13], v[54:55]
; GFX10-NEXT: v_max_f64 v[54:55], v[14:15], v[52:53]
; GFX10-NEXT: s_waitcnt vmcnt(11)
; GFX10-NEXT: v_max_f64 v[64:65], v[20:21], v[70:71]
-; GFX10-NEXT: v_cmp_u_f64_e64 s13, v[20:21], v[70:71]
+; GFX10-NEXT: v_cmp_o_f64_e64 s13, v[20:21], v[70:71]
; GFX10-NEXT: s_waitcnt vmcnt(9)
-; GFX10-NEXT: v_cmp_u_f64_e64 s12, v[18:19], v[80:81]
+; GFX10-NEXT: v_cmp_o_f64_e64 s12, v[18:19], v[80:81]
; GFX10-NEXT: s_waitcnt vmcnt(8)
; GFX10-NEXT: v_max_f64 v[52:53], v[16:17], v[50:51]
-; GFX10-NEXT: v_cmp_u_f64_e64 s11, v[16:17], v[50:51]
+; GFX10-NEXT: v_cmp_o_f64_e64 s11, v[16:17], v[50:51]
; GFX10-NEXT: v_max_f64 v[50:51], v[18:19], v[80:81]
; GFX10-NEXT: v_max_f64 v[70:71], v[22:23], v[68:69]
-; GFX10-NEXT: v_cmp_u_f64_e64 s14, v[22:23], v[68:69]
+; GFX10-NEXT: v_cmp_o_f64_e64 s14, v[22:23], v[68:69]
; GFX10-NEXT: s_waitcnt vmcnt(7)
; GFX10-NEXT: v_max_f64 v[68:69], v[24:25], v[66:67]
-; GFX10-NEXT: v_cmp_u_f64_e64 s15, v[24:25], v[66:67]
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v34, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v35, 0x7ff80000, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v48, 0, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v49, 0x7ff80000, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v36, 0, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v37, 0x7ff80000, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v38, 0, s9
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v39, 0x7ff80000, s9
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v54, 0, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v55, 0x7ff80000, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v16, v52, 0, s11
-; GFX10-NEXT: v_cndmask_b32_e64 v17, v53, 0x7ff80000, s11
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v50, 0, s12
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v51, 0x7ff80000, s12
-; GFX10-NEXT: v_cndmask_b32_e64 v20, v64, 0, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v21, v65, 0x7ff80000, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v70, 0, s14
-; GFX10-NEXT: v_cndmask_b32_e64 v23, v71, 0x7ff80000, s14
-; GFX10-NEXT: v_cndmask_b32_e64 v24, v68, 0, s15
-; GFX10-NEXT: v_cndmask_b32_e64 v25, v69, 0x7ff80000, s15
+; GFX10-NEXT: v_cmp_o_f64_e64 s15, v[24:25], v[66:67]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v34, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v35, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v48, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0x7ff80000, v49, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v36, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0x7ff80000, v37, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, v38, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v13, 0x7ff80000, v39, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, v54, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v15, 0x7ff80000, v55, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, v52, s11
+; GFX10-NEXT: v_cndmask_b32_e64 v17, 0x7ff80000, v53, s11
+; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, v50, s12
+; GFX10-NEXT: v_cndmask_b32_e64 v19, 0x7ff80000, v51, s12
+; GFX10-NEXT: v_cndmask_b32_e64 v20, 0, v64, s13
+; GFX10-NEXT: v_cndmask_b32_e64 v21, 0x7ff80000, v65, s13
+; GFX10-NEXT: v_cndmask_b32_e64 v22, 0, v70, s14
+; GFX10-NEXT: v_cndmask_b32_e64 v23, 0x7ff80000, v71, s14
+; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, v68, s15
+; GFX10-NEXT: v_cndmask_b32_e64 v25, 0x7ff80000, v69, s15
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_max_f64 v[80:81], v[28:29], v[0:1]
-; GFX10-NEXT: v_cmp_u_f64_e64 s17, v[28:29], v[0:1]
+; GFX10-NEXT: v_cmp_o_f64_e64 s17, v[28:29], v[0:1]
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_max_f64 v[66:67], v[26:27], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e64 s16, v[26:27], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v82, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e64 s16, v[26:27], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v82, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_max_f64 v[86:87], v[30:31], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e64 s18, v[30:31], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v83, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v84, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v85, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v32, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v33, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v28, v80, 0, s17
-; GFX10-NEXT: v_cndmask_b32_e64 v29, v81, 0x7ff80000, s17
-; GFX10-NEXT: v_cndmask_b32_e64 v26, v66, 0, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v27, v67, 0x7ff80000, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v30, v86, 0, s18
-; GFX10-NEXT: v_cndmask_b32_e64 v31, v87, 0x7ff80000, s18
+; GFX10-NEXT: v_cmp_o_f64_e64 s18, v[30:31], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v83, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v84, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v85, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v33, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v28, 0, v80, s17
+; GFX10-NEXT: v_cndmask_b32_e64 v29, 0x7ff80000, v81, s17
+; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, v66, s16
+; GFX10-NEXT: v_cndmask_b32_e64 v27, 0x7ff80000, v67, s16
+; GFX10-NEXT: v_cndmask_b32_e64 v30, 0, v86, s18
+; GFX10-NEXT: v_cndmask_b32_e64 v31, 0x7ff80000, v87, s18
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v16f64:
@@ -2678,84 +2678,84 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:124
; GFX11-NEXT: s_waitcnt vmcnt(30)
; GFX11-NEXT: v_max_f64 v[96:97], v[0:1], v[32:33]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[32:33]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[32:33]
; GFX11-NEXT: s_waitcnt vmcnt(28)
; GFX11-NEXT: v_max_f64 v[32:33], v[2:3], v[34:35]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[34:35]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[34:35]
; GFX11-NEXT: s_waitcnt vmcnt(26)
; GFX11-NEXT: v_max_f64 v[34:35], v[4:5], v[36:37]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[36:37]
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[36:37]
; GFX11-NEXT: s_waitcnt vmcnt(24)
; GFX11-NEXT: v_max_f64 v[36:37], v[6:7], v[38:39]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[38:39]
+; GFX11-NEXT: v_cmp_o_f64_e64 s2, v[6:7], v[38:39]
; GFX11-NEXT: s_waitcnt vmcnt(22)
; GFX11-NEXT: v_max_f64 v[38:39], v[8:9], v[48:49]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[8:9], v[48:49]
+; GFX11-NEXT: v_cmp_o_f64_e64 s3, v[8:9], v[48:49]
; GFX11-NEXT: s_waitcnt vmcnt(20)
; GFX11-NEXT: v_max_f64 v[48:49], v[10:11], v[50:51]
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[10:11], v[50:51]
+; GFX11-NEXT: v_cmp_o_f64_e64 s4, v[10:11], v[50:51]
; GFX11-NEXT: s_waitcnt vmcnt(18)
; GFX11-NEXT: v_max_f64 v[50:51], v[12:13], v[52:53]
-; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[52:53]
+; GFX11-NEXT: v_cmp_o_f64_e64 s5, v[12:13], v[52:53]
; GFX11-NEXT: s_waitcnt vmcnt(16)
; GFX11-NEXT: v_max_f64 v[52:53], v[14:15], v[54:55]
-; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[54:55]
+; GFX11-NEXT: v_cmp_o_f64_e64 s6, v[14:15], v[54:55]
; GFX11-NEXT: s_waitcnt vmcnt(14)
; GFX11-NEXT: v_max_f64 v[54:55], v[16:17], v[64:65]
-; GFX11-NEXT: v_cmp_u_f64_e64 s7, v[16:17], v[64:65]
+; GFX11-NEXT: v_cmp_o_f64_e64 s7, v[16:17], v[64:65]
; GFX11-NEXT: s_waitcnt vmcnt(12)
; GFX11-NEXT: v_max_f64 v[64:65], v[18:19], v[66:67]
-; GFX11-NEXT: v_cmp_u_f64_e64 s8, v[18:19], v[66:67]
+; GFX11-NEXT: v_cmp_o_f64_e64 s8, v[18:19], v[66:67]
; GFX11-NEXT: s_waitcnt vmcnt(10)
; GFX11-NEXT: v_max_f64 v[66:67], v[20:21], v[68:69]
-; GFX11-NEXT: v_cmp_u_f64_e64 s9, v[20:21], v[68:69]
+; GFX11-NEXT: v_cmp_o_f64_e64 s9, v[20:21], v[68:69]
; GFX11-NEXT: s_waitcnt vmcnt(8)
; GFX11-NEXT: v_max_f64 v[68:69], v[22:23], v[70:71]
-; GFX11-NEXT: v_cmp_u_f64_e64 s10, v[22:23], v[70:71]
+; GFX11-NEXT: v_cmp_o_f64_e64 s10, v[22:23], v[70:71]
; GFX11-NEXT: s_waitcnt vmcnt(6)
; GFX11-NEXT: v_max_f64 v[70:71], v[24:25], v[80:81]
-; GFX11-NEXT: v_cmp_u_f64_e64 s11, v[24:25], v[80:81]
+; GFX11-NEXT: v_cmp_o_f64_e64 s11, v[24:25], v[80:81]
; GFX11-NEXT: s_waitcnt vmcnt(4)
; GFX11-NEXT: v_max_f64 v[80:81], v[26:27], v[82:83]
-; GFX11-NEXT: v_cmp_u_f64_e64 s12, v[26:27], v[82:83]
+; GFX11-NEXT: v_cmp_o_f64_e64 s12, v[26:27], v[82:83]
; GFX11-NEXT: s_waitcnt vmcnt(2)
; GFX11-NEXT: v_max_f64 v[82:83], v[28:29], v[84:85]
-; GFX11-NEXT: v_cmp_u_f64_e64 s13, v[28:29], v[84:85]
+; GFX11-NEXT: v_cmp_o_f64_e64 s13, v[28:29], v[84:85]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f64 v[84:85], v[30:31], v[86:87]
-; GFX11-NEXT: v_cmp_u_f64_e64 s14, v[30:31], v[86:87]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v96, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v97, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v32, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v33, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v34, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v35, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v36, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v37, 0x7ff80000, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v38, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v39, 0x7ff80000, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v48, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v49, 0x7ff80000, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v50, 0, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v51, 0x7ff80000, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v52, 0, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v53, 0x7ff80000, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v16, v54, 0, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v17, v55, 0x7ff80000, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v18, v64, 0, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v19, v65, 0x7ff80000, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v20, v66, 0, s9
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v67, 0x7ff80000, s9
-; GFX11-NEXT: v_cndmask_b32_e64 v22, v68, 0, s10
-; GFX11-NEXT: v_cndmask_b32_e64 v23, v69, 0x7ff80000, s10
-; GFX11-NEXT: v_cndmask_b32_e64 v24, v70, 0, s11
-; GFX11-NEXT: v_cndmask_b32_e64 v25, v71, 0x7ff80000, s11
-; GFX11-NEXT: v_cndmask_b32_e64 v26, v80, 0, s12
-; GFX11-NEXT: v_cndmask_b32_e64 v27, v81, 0x7ff80000, s12
-; GFX11-NEXT: v_cndmask_b32_e64 v28, v82, 0, s13
-; GFX11-NEXT: v_cndmask_b32_e64 v29, v83, 0x7ff80000, s13
-; GFX11-NEXT: v_cndmask_b32_e64 v30, v84, 0, s14
-; GFX11-NEXT: v_cndmask_b32_e64 v31, v85, 0x7ff80000, s14
+; GFX11-NEXT: v_cmp_o_f64_e64 s14, v[30:31], v[86:87]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v96, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v97, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v33, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v34, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v35, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v36, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v37, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v38, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0x7ff80000, v39, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v48, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v11, 0x7ff80000, v49, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, v50, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v13, 0x7ff80000, v51, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v14, 0, v52, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v15, 0x7ff80000, v53, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v16, 0, v54, s7
+; GFX11-NEXT: v_cndmask_b32_e64 v17, 0x7ff80000, v55, s7
+; GFX11-NEXT: v_cndmask_b32_e64 v18, 0, v64, s8
+; GFX11-NEXT: v_cndmask_b32_e64 v19, 0x7ff80000, v65, s8
+; GFX11-NEXT: v_cndmask_b32_e64 v20, 0, v66, s9
+; GFX11-NEXT: v_cndmask_b32_e64 v21, 0x7ff80000, v67, s9
+; GFX11-NEXT: v_cndmask_b32_e64 v22, 0, v68, s10
+; GFX11-NEXT: v_cndmask_b32_e64 v23, 0x7ff80000, v69, s10
+; GFX11-NEXT: v_cndmask_b32_e64 v24, 0, v70, s11
+; GFX11-NEXT: v_cndmask_b32_e64 v25, 0x7ff80000, v71, s11
+; GFX11-NEXT: v_cndmask_b32_e64 v26, 0, v80, s12
+; GFX11-NEXT: v_cndmask_b32_e64 v27, 0x7ff80000, v81, s12
+; GFX11-NEXT: v_cndmask_b32_e64 v28, 0, v82, s13
+; GFX11-NEXT: v_cndmask_b32_e64 v29, 0x7ff80000, v83, s13
+; GFX11-NEXT: v_cndmask_b32_e64 v30, 0, v84, s14
+; GFX11-NEXT: v_cndmask_b32_e64 v31, 0x7ff80000, v85, s14
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v16f64:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
index 4c413af878462..e7a22329388ef 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
@@ -13,60 +13,60 @@ define double @v_minimum_f64(double %src0, double %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_f64:
@@ -131,60 +131,60 @@ define double @v_minimum_f64__nsz(double %src0, double %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_f64__nsz:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_f64__nsz:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_f64__nsz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_f64__nsz:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_f64__nsz:
@@ -250,10 +250,10 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_f64__nnan_src0:
@@ -261,10 +261,10 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_f64__nnan_src0:
@@ -272,10 +272,10 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX900-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_f64__nnan_src0:
@@ -283,11 +283,11 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) {
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX950-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_f64__nnan_src0:
@@ -295,9 +295,9 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_f64__nnan_src0:
@@ -306,10 +306,10 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) {
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_f64__nnan_src0:
@@ -334,10 +334,10 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_f64__nnan_src1:
@@ -345,10 +345,10 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_f64__nnan_src1:
@@ -356,10 +356,10 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX900-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_f64__nnan_src1:
@@ -367,11 +367,11 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) {
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX950-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_f64__nnan_src1:
@@ -379,9 +379,9 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_f64__nnan_src1:
@@ -390,10 +390,10 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) {
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_f64__nnan_src1:
@@ -520,85 +520,85 @@ define <2 x double> @v_minimum_v2f64(<2 x double> %src0, <2 x double> %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX7-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v2f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX8-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v2f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX900-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX900-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v2f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX950-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX950-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[6:7]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v8, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_v2f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX10-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v5, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v2f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX11-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v5, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_v2f64:
@@ -670,85 +670,85 @@ define <2 x double> @v_minimum_v2f64__nsz(<2 x double> %src0, <2 x double> %src1
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX7-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v2f64__nsz:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX8-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v2f64__nsz:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX900-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[6:7]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[6:7]
; GFX900-NEXT: v_mov_b32_e32 v3, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[4:5]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v2f64__nsz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX950-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX950-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[6:7]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v8, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_v2f64__nsz:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX10-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v5, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v2f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX11-NEXT: v_min_f64 v[4:5], v[2:3], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v5, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_v2f64__nsz:
@@ -955,109 +955,109 @@ define <3 x double> @v_minimum_v3f64(<3 x double> %src0, <3 x double> %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX7-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX7-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX7-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v3f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX8-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX8-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX8-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v3f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX900-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX900-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX900-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v3f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX950-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
; GFX950-NEXT: v_mov_b32_e32 v12, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v13, v12, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v12, v13, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[8:9]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v7, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v7, vcc
; GFX950-NEXT: v_min_f64 v[6:7], v[4:5], v[10:11]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[10:11]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v12, v7, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_v3f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX10-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[8:9]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[8:9]
; GFX10-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s5
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v7, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v9, s5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v3f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX11-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[8:9]
; GFX11-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s1
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v13, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v7, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v8, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v9, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_v3f64:
@@ -1136,109 +1136,109 @@ define <3 x double> @v_minimum_v3f64__nsz(<3 x double> %src0, <3 x double> %src1
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX7-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX7-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX7-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v3f64__nsz:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX8-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX8-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX8-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v3f64__nsz:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX900-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[8:9]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[8:9]
; GFX900-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[10:11]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[10:11]
; GFX900-NEXT: v_mov_b32_e32 v5, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v13, v5, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v13, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v8, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v3f64__nsz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX950-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc
; GFX950-NEXT: v_mov_b32_e32 v12, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v13, v12, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[8:9]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v12, v13, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[8:9]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v7, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v7, vcc
; GFX950-NEXT: v_min_f64 v[6:7], v[4:5], v[10:11]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[10:11]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[10:11]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v12, v7, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_v3f64__nsz:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX10-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[8:9]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[8:9]
; GFX10-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s5
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v7, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v9, s5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v3f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[12:13], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX11-NEXT: v_min_f64 v[6:7], v[2:3], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[8:9]
; GFX11-NEXT: v_min_f64 v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v13, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, 0x7ff80000, s1
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v12, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v13, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v7, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v8, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v9, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_v3f64__nsz:
@@ -1317,134 +1317,134 @@ define <4 x double> @v_minimum_v4f64(<4 x double> %src0, <4 x double> %src1) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX7-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX7-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX7-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX7-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v4f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX8-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX8-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX8-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX8-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v4f64:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX900-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX900-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX900-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX900-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v4f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX950-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX950-NEXT: v_mov_b32_e32 v16, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[10:11]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[10:11]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v16, v9, vcc
; GFX950-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[12:13]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v16, v9, vcc
; GFX950-NEXT: v_min_f64 v[8:9], v[6:7], v[14:15]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[6:7], v[14:15]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v16, v9, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_v4f64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX10-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[10:11]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[10:11]
; GFX10-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[12:13]
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[12:13]
; GFX10-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cmp_o_f64_e64 s6, v[6:7], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v10, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v11, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v12, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v13, s6
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX11-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[10:11]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[10:11]
; GFX11-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[12:13]
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[12:13]
; GFX11-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cmp_o_f64_e64 s2, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v8, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v9, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v10, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v11, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v12, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v13, s2
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_v4f64:
@@ -1530,134 +1530,134 @@ define <4 x double> @v_minimum_v4f64__nsz(<4 x double> %src0, <4 x double> %src1
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX7-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX7-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX7-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX7-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v4f64__nsz:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX8-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX8-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX8-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX8-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v4f64__nsz:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX900-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[10:11]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[10:11]
; GFX900-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[12:13]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[12:13]
; GFX900-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[14:15]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[14:15]
; GFX900-NEXT: v_mov_b32_e32 v7, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v17, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v7, v9, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[8:9]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v4f64__nsz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX950-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX950-NEXT: v_mov_b32_e32 v16, 0x7ff80000
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[10:11]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v16, v17, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[10:11]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v16, v9, vcc
; GFX950-NEXT: v_min_f64 v[8:9], v[4:5], v[12:13]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[12:13]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v16, v9, vcc
; GFX950-NEXT: v_min_f64 v[8:9], v[6:7], v[14:15]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[6:7], v[14:15]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v16, v9, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_v4f64__nsz:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX10-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[10:11]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[10:11]
; GFX10-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[12:13]
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[12:13]
; GFX10-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cmp_o_f64_e64 s6, v[6:7], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v9, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v10, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v11, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v12, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v13, s6
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v4f64__nsz:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[16:17], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX11-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[10:11]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[10:11]
; GFX11-NEXT: v_min_f64 v[10:11], v[4:5], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[12:13]
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[12:13]
; GFX11-NEXT: v_min_f64 v[12:13], v[6:7], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cmp_o_f64_e64 s2, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v8, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v9, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v10, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v11, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v12, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v13, s2
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_v4f64__nsz:
@@ -1744,39 +1744,39 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX7-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[18:19]
; GFX7-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX7-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX7-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX7-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[24:25]
; GFX7-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[26:27]
; GFX7-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[28:29]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v34, v33, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v16, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v34, v17, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v18, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v34, v19, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, v20, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v34, v21, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, v22, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v34, v23, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, v24, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v34, v25, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v12, 0, v26, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v13, v34, v27, s[14:15]
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_min_f64 v[16:17], v[14:15], v[30:31]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
-; GFX7-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[30:31]
+; GFX7-NEXT: v_cndmask_b32_e32 v14, 0, v16, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v15, v34, v17, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v8f64:
@@ -1784,39 +1784,39 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX8-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[18:19]
; GFX8-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX8-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX8-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX8-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[24:25]
; GFX8-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[26:27]
; GFX8-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[28:29]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v34, v33, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v16, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v34, v17, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v18, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v34, v19, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v20, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v34, v21, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v22, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v34, v23, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v24, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v34, v25, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, v26, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v34, v27, s[14:15]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_min_f64 v[16:17], v[14:15], v[30:31]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
-; GFX8-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[30:31]
+; GFX8-NEXT: v_cndmask_b32_e32 v14, 0, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v34, v17, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v8f64:
@@ -1824,39 +1824,39 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX900-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX900-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[18:19]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[18:19]
; GFX900-NEXT: v_mov_b32_e32 v34, 0x7ff80000
; GFX900-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[20:21]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[20:21]
; GFX900-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[22:23]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[22:23]
; GFX900-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[24:25]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[24:25]
; GFX900-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[26:27]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[26:27]
; GFX900-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[28:29]
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v17, v34, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v18, 0, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v19, v34, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v20, 0, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v21, v34, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v8, v22, 0, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v9, v23, v34, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v10, v24, 0, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v11, v25, v34, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v12, v26, 0, s[14:15]
-; GFX900-NEXT: v_cndmask_b32_e64 v13, v27, v34, s[14:15]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[28:29]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v34, v33, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v16, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v34, v17, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v18, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v34, v19, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, 0, v20, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v34, v21, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v8, 0, v22, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v9, v34, v23, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v10, 0, v24, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v11, v34, v25, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v12, 0, v26, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v13, v34, v27, s[14:15]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_min_f64 v[16:17], v[14:15], v[30:31]
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
-; GFX900-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v15, v17, v34, vcc
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[30:31]
+; GFX900-NEXT: v_cndmask_b32_e32 v14, 0, v16, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v15, v34, v17, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v8f64:
@@ -1865,42 +1865,42 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX950-NEXT: scratch_load_dword v31, off, s32
; GFX950-NEXT: v_mov_b32_e32 v54, 0x7ff80000
; GFX950-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX950-NEXT: v_min_f64 v[34:35], v[2:3], v[18:19]
; GFX950-NEXT: v_min_f64 v[36:37], v[4:5], v[20:21]
-; GFX950-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v33, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[18:19]
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v54, v33, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[2:3], v[18:19]
; GFX950-NEXT: v_min_f64 v[38:39], v[6:7], v[22:23]
; GFX950-NEXT: v_min_f64 v[48:49], v[8:9], v[24:25]
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v34, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v35, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[20:21]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v34, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v54, v35, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[4:5], v[20:21]
; GFX950-NEXT: v_min_f64 v[50:51], v[10:11], v[26:27]
; GFX950-NEXT: v_min_f64 v[52:53], v[12:13], v[28:29]
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v36, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v37, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[22:23]
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v36, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v54, v37, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[6:7], v[22:23]
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_min_f64 v[16:17], v[14:15], v[30:31]
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v38, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v7, v39, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v38, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v54, v39, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[8:9], v[24:25]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v8, v48, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v9, v49, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX950-NEXT: v_cndmask_b32_e32 v8, 0, v48, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v9, v54, v49, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[10:11], v[26:27]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v10, v50, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v11, v51, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v50, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v11, v54, v51, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[12:13], v[28:29]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v12, v52, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v13, v53, v54, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[30:31]
+; GFX950-NEXT: v_cndmask_b32_e32 v12, 0, v52, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v13, v54, v53, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[30:31]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v15, v17, v54, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v14, 0, v16, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v15, v54, v17, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minimum_v8f64:
@@ -1908,38 +1908,38 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[16:17]
; GFX10-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[18:19]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[18:19]
; GFX10-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[20:21]
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[20:21]
; GFX10-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[22:23]
+; GFX10-NEXT: v_cmp_o_f64_e64 s6, v[6:7], v[22:23]
; GFX10-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX10-NEXT: v_cmp_u_f64_e64 s7, v[8:9], v[24:25]
+; GFX10-NEXT: v_cmp_o_f64_e64 s7, v[8:9], v[24:25]
; GFX10-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX10-NEXT: v_cmp_u_f64_e64 s8, v[10:11], v[26:27]
+; GFX10-NEXT: v_cmp_o_f64_e64 s8, v[10:11], v[26:27]
; GFX10-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX10-NEXT: v_cmp_u_f64_e64 s9, v[12:13], v[28:29]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v33, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v16, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v17, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v19, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v20, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v21, 0x7ff80000, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v22, 0, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v23, 0x7ff80000, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v24, 0, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v25, 0x7ff80000, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v26, 0, s9
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v27, 0x7ff80000, s9
+; GFX10-NEXT: v_cmp_o_f64_e64 s9, v[12:13], v[28:29]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v33, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v16, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v17, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v18, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v19, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v20, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v21, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v22, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0x7ff80000, v23, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v24, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0x7ff80000, v25, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, v26, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v13, 0x7ff80000, v27, s9
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_min_f64 v[28:29], v[14:15], v[30:31]
-; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[30:31]
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v28, 0, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v29, 0x7ff80000, s10
+; GFX10-NEXT: v_cmp_o_f64_e64 s10, v[14:15], v[30:31]
+; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, v28, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v15, 0x7ff80000, v29, s10
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v8f64:
@@ -1947,39 +1947,39 @@ define <8 x double> @v_minimum_v8f64(<8 x double> %src0, <8 x double> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_min_f64 v[32:33], v[0:1], v[16:17]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[16:17]
; GFX11-NEXT: v_min_f64 v[16:17], v[2:3], v[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[18:19]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[18:19]
; GFX11-NEXT: v_min_f64 v[18:19], v[4:5], v[20:21]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[20:21]
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[20:21]
; GFX11-NEXT: v_min_f64 v[20:21], v[6:7], v[22:23]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[22:23]
+; GFX11-NEXT: v_cmp_o_f64_e64 s2, v[6:7], v[22:23]
; GFX11-NEXT: v_min_f64 v[22:23], v[8:9], v[24:25]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[8:9], v[24:25]
+; GFX11-NEXT: v_cmp_o_f64_e64 s3, v[8:9], v[24:25]
; GFX11-NEXT: v_min_f64 v[24:25], v[10:11], v[26:27]
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[10:11], v[26:27]
+; GFX11-NEXT: v_cmp_o_f64_e64 s4, v[10:11], v[26:27]
; GFX11-NEXT: v_min_f64 v[26:27], v[12:13], v[28:29]
-; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[28:29]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v33, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v16, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v17, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v18, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v19, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v20, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v21, 0x7ff80000, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v22, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v23, 0x7ff80000, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v24, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v25, 0x7ff80000, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v26, 0, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v27, 0x7ff80000, s5
+; GFX11-NEXT: v_cmp_o_f64_e64 s5, v[12:13], v[28:29]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v33, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v16, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v17, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v18, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v19, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v20, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v21, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v22, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0x7ff80000, v23, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v24, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v11, 0x7ff80000, v25, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, v26, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v13, 0x7ff80000, v27, s5
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_min_f64 v[28:29], v[14:15], v[30:31]
-; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[30:31]
+; GFX11-NEXT: v_cmp_o_f64_e64 s6, v[14:15], v[30:31]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v28, 0, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v29, 0x7ff80000, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v14, 0, v28, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v15, 0x7ff80000, v29, s6
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_v8f64:
@@ -2011,117 +2011,117 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[31:32]
; GFX7-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[31:32]
; GFX7-NEXT: v_min_f64 v[2:3], v[2:3], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[31:32]
; GFX7-NEXT: v_min_f64 v[4:5], v[4:5], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[31:32]
; GFX7-NEXT: v_min_f64 v[6:7], v[6:7], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[31:32]
; GFX7-NEXT: v_min_f64 v[8:9], v[8:9], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[10:11]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[31:32]
; GFX7-NEXT: v_min_f64 v[10:11], v[10:11], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[12:13]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[31:32]
; GFX7-NEXT: v_min_f64 v[12:13], v[12:13], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX7-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[14:15]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[16:17], v[14:15], v[31:32]
; GFX7-NEXT: v_min_f64 v[14:15], v[14:15], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX7-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX7-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[16:17]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[18:19], v[16:17], v[31:32]
; GFX7-NEXT: v_min_f64 v[16:17], v[16:17], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX7-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX7-NEXT: v_cndmask_b32_e64 v16, 0, v16, s[18:19]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[20:21], v[18:19], v[31:32]
; GFX7-NEXT: v_min_f64 v[18:19], v[18:19], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX7-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX7-NEXT: v_cndmask_b32_e64 v18, 0, v18, s[20:21]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[22:23], v[20:21], v[31:32]
; GFX7-NEXT: v_min_f64 v[20:21], v[20:21], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX7-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v20, 0, v20, s[22:23]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[24:25], v[22:23], v[31:32]
; GFX7-NEXT: v_min_f64 v[22:23], v[22:23], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX7-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX7-NEXT: v_cndmask_b32_e64 v22, 0, v22, s[24:25]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[26:27], v[24:25], v[31:32]
; GFX7-NEXT: v_min_f64 v[24:25], v[24:25], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX7-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, v24, s[26:27]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[28:29], v[26:27], v[31:32]
; GFX7-NEXT: v_min_f64 v[26:27], v[26:27], v[31:32]
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX7-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX7-NEXT: v_cndmask_b32_e64 v26, 0, v26, s[28:29]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[40:41], v[28:29], v[31:32]
; GFX7-NEXT: v_min_f64 v[28:29], v[28:29], v[31:32]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX7-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX7-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e64 v28, 0, v28, s[40:41]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
+; GFX7-NEXT: v_cmp_o_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX7-NEXT: v_min_f64 v[30:31], v[30:31], v[32:33]
; GFX7-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX7-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX7-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX7-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX7-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX7-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX7-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX7-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
-; GFX7-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
-; GFX7-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v32, v3, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v32, v5, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v32, v7, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v32, v9, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v32, v11, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v13, v32, v13, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v15, v32, v15, s[16:17]
+; GFX7-NEXT: v_cndmask_b32_e64 v17, v32, v17, s[18:19]
+; GFX7-NEXT: v_cndmask_b32_e64 v19, v32, v19, s[20:21]
+; GFX7-NEXT: v_cndmask_b32_e64 v21, v32, v21, s[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v23, v32, v23, s[24:25]
+; GFX7-NEXT: v_cndmask_b32_e64 v25, v32, v25, s[26:27]
+; GFX7-NEXT: v_cndmask_b32_e64 v27, v32, v27, s[28:29]
+; GFX7-NEXT: v_cndmask_b32_e64 v29, v32, v29, s[40:41]
+; GFX7-NEXT: v_cndmask_b32_e64 v31, v32, v31, s[42:43]
+; GFX7-NEXT: v_cndmask_b32_e64 v30, 0, v30, s[42:43]
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_minimum_v16f64:
@@ -2130,117 +2130,117 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[31:32]
; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[31:32]
; GFX8-NEXT: v_min_f64 v[2:3], v[2:3], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[31:32]
; GFX8-NEXT: v_min_f64 v[4:5], v[4:5], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[31:32]
; GFX8-NEXT: v_min_f64 v[6:7], v[6:7], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[31:32]
; GFX8-NEXT: v_min_f64 v[8:9], v[8:9], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[10:11]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[31:32]
; GFX8-NEXT: v_min_f64 v[10:11], v[10:11], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[12:13]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[31:32]
; GFX8-NEXT: v_min_f64 v[12:13], v[12:13], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[14:15]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[16:17], v[14:15], v[31:32]
; GFX8-NEXT: v_min_f64 v[14:15], v[14:15], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[16:17]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[18:19], v[16:17], v[31:32]
; GFX8-NEXT: v_min_f64 v[16:17], v[16:17], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v16, 0, v16, s[18:19]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[20:21], v[18:19], v[31:32]
; GFX8-NEXT: v_min_f64 v[18:19], v[18:19], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v18, 0, v18, s[20:21]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[22:23], v[20:21], v[31:32]
; GFX8-NEXT: v_min_f64 v[20:21], v[20:21], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v20, 0, v20, s[22:23]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[24:25], v[22:23], v[31:32]
; GFX8-NEXT: v_min_f64 v[22:23], v[22:23], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v22, 0, v22, s[24:25]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[26:27], v[24:25], v[31:32]
; GFX8-NEXT: v_min_f64 v[24:25], v[24:25], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, v24, s[26:27]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[28:29], v[26:27], v[31:32]
; GFX8-NEXT: v_min_f64 v[26:27], v[26:27], v[31:32]
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v26, 0, v26, s[28:29]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[40:41], v[28:29], v[31:32]
; GFX8-NEXT: v_min_f64 v[28:29], v[28:29], v[31:32]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX8-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e64 v28, 0, v28, s[40:41]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
+; GFX8-NEXT: v_cmp_o_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX8-NEXT: v_min_f64 v[30:31], v[30:31], v[32:33]
; GFX8-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX8-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX8-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX8-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX8-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX8-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
-; GFX8-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
-; GFX8-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v32, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v32, v5, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v32, v7, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v32, v9, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v32, v11, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v32, v13, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v15, v32, v15, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v17, v32, v17, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v19, v32, v19, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v21, v32, v21, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v23, v32, v23, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v25, v32, v25, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v27, v32, v27, s[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v29, v32, v29, s[40:41]
+; GFX8-NEXT: v_cndmask_b32_e64 v31, v32, v31, s[42:43]
+; GFX8-NEXT: v_cndmask_b32_e64 v30, 0, v30, s[42:43]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_minimum_v16f64:
@@ -2249,117 +2249,117 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[31:32]
; GFX900-NEXT: v_min_f64 v[0:1], v[0:1], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:16
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[4:5], v[2:3], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[4:5], v[2:3], v[31:32]
; GFX900-NEXT: v_min_f64 v[2:3], v[2:3], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
-; GFX900-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[6:7], v[4:5], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[6:7], v[4:5], v[31:32]
; GFX900-NEXT: v_min_f64 v[4:5], v[4:5], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
-; GFX900-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[6:7]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[8:9], v[6:7], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[8:9], v[6:7], v[31:32]
; GFX900-NEXT: v_min_f64 v[6:7], v[6:7], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
-; GFX900-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[8:9]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[10:11], v[8:9], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[10:11], v[8:9], v[31:32]
; GFX900-NEXT: v_min_f64 v[8:9], v[8:9], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
-; GFX900-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[10:11]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[12:13], v[10:11], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[12:13], v[10:11], v[31:32]
; GFX900-NEXT: v_min_f64 v[10:11], v[10:11], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:56
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
-; GFX900-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[12:13]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[14:15], v[12:13], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[14:15], v[12:13], v[31:32]
; GFX900-NEXT: v_min_f64 v[12:13], v[12:13], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
-; GFX900-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[14:15]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[16:17], v[14:15], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[16:17], v[14:15], v[31:32]
; GFX900-NEXT: v_min_f64 v[14:15], v[14:15], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; GFX900-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[16:17]
+; GFX900-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[18:19], v[16:17], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[18:19], v[16:17], v[31:32]
; GFX900-NEXT: v_min_f64 v[16:17], v[16:17], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; GFX900-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[18:19]
+; GFX900-NEXT: v_cndmask_b32_e64 v16, 0, v16, s[18:19]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[20:21], v[18:19], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[20:21], v[18:19], v[31:32]
; GFX900-NEXT: v_min_f64 v[18:19], v[18:19], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
-; GFX900-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[20:21]
+; GFX900-NEXT: v_cndmask_b32_e64 v18, 0, v18, s[20:21]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[22:23], v[20:21], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[22:23], v[20:21], v[31:32]
; GFX900-NEXT: v_min_f64 v[20:21], v[20:21], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; GFX900-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[22:23]
+; GFX900-NEXT: v_cndmask_b32_e64 v20, 0, v20, s[22:23]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[24:25], v[22:23], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[24:25], v[22:23], v[31:32]
; GFX900-NEXT: v_min_f64 v[22:23], v[22:23], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104
-; GFX900-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[24:25]
+; GFX900-NEXT: v_cndmask_b32_e64 v22, 0, v22, s[24:25]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[26:27], v[24:25], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[26:27], v[24:25], v[31:32]
; GFX900-NEXT: v_min_f64 v[24:25], v[24:25], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
-; GFX900-NEXT: v_cndmask_b32_e64 v24, v24, 0, s[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v24, 0, v24, s[26:27]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[28:29], v[26:27], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[28:29], v[26:27], v[31:32]
; GFX900-NEXT: v_min_f64 v[26:27], v[26:27], v[31:32]
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:120
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
-; GFX900-NEXT: v_cndmask_b32_e64 v26, v26, 0, s[28:29]
+; GFX900-NEXT: v_cndmask_b32_e64 v26, 0, v26, s[28:29]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[40:41], v[28:29], v[31:32]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[40:41], v[28:29], v[31:32]
; GFX900-NEXT: v_min_f64 v[28:29], v[28:29], v[31:32]
; GFX900-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX900-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
; GFX900-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
-; GFX900-NEXT: v_cndmask_b32_e64 v28, v28, 0, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e64 v28, 0, v28, s[40:41]
; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_cmp_u_f64_e64 s[42:43], v[30:31], v[32:33]
+; GFX900-NEXT: v_cmp_o_f64_e64 s[42:43], v[30:31], v[32:33]
; GFX900-NEXT: v_min_f64 v[30:31], v[30:31], v[32:33]
; GFX900-NEXT: v_mov_b32_e32 v32, 0x7ff80000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v32, vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v3, v3, v32, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e64 v5, v5, v32, s[6:7]
-; GFX900-NEXT: v_cndmask_b32_e64 v7, v7, v32, s[8:9]
-; GFX900-NEXT: v_cndmask_b32_e64 v9, v9, v32, s[10:11]
-; GFX900-NEXT: v_cndmask_b32_e64 v11, v11, v32, s[12:13]
-; GFX900-NEXT: v_cndmask_b32_e64 v13, v13, v32, s[14:15]
-; GFX900-NEXT: v_cndmask_b32_e64 v15, v15, v32, s[16:17]
-; GFX900-NEXT: v_cndmask_b32_e64 v17, v17, v32, s[18:19]
-; GFX900-NEXT: v_cndmask_b32_e64 v19, v19, v32, s[20:21]
-; GFX900-NEXT: v_cndmask_b32_e64 v21, v21, v32, s[22:23]
-; GFX900-NEXT: v_cndmask_b32_e64 v23, v23, v32, s[24:25]
-; GFX900-NEXT: v_cndmask_b32_e64 v25, v25, v32, s[26:27]
-; GFX900-NEXT: v_cndmask_b32_e64 v27, v27, v32, s[28:29]
-; GFX900-NEXT: v_cndmask_b32_e64 v29, v29, v32, s[40:41]
-; GFX900-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[42:43]
-; GFX900-NEXT: v_cndmask_b32_e64 v30, v30, 0, s[42:43]
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v32, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e64 v3, v32, v3, s[4:5]
+; GFX900-NEXT: v_cndmask_b32_e64 v5, v32, v5, s[6:7]
+; GFX900-NEXT: v_cndmask_b32_e64 v7, v32, v7, s[8:9]
+; GFX900-NEXT: v_cndmask_b32_e64 v9, v32, v9, s[10:11]
+; GFX900-NEXT: v_cndmask_b32_e64 v11, v32, v11, s[12:13]
+; GFX900-NEXT: v_cndmask_b32_e64 v13, v32, v13, s[14:15]
+; GFX900-NEXT: v_cndmask_b32_e64 v15, v32, v15, s[16:17]
+; GFX900-NEXT: v_cndmask_b32_e64 v17, v32, v17, s[18:19]
+; GFX900-NEXT: v_cndmask_b32_e64 v19, v32, v19, s[20:21]
+; GFX900-NEXT: v_cndmask_b32_e64 v21, v32, v21, s[22:23]
+; GFX900-NEXT: v_cndmask_b32_e64 v23, v32, v23, s[24:25]
+; GFX900-NEXT: v_cndmask_b32_e64 v25, v32, v25, s[26:27]
+; GFX900-NEXT: v_cndmask_b32_e64 v27, v32, v27, s[28:29]
+; GFX900-NEXT: v_cndmask_b32_e64 v29, v32, v29, s[40:41]
+; GFX900-NEXT: v_cndmask_b32_e64 v31, v32, v31, s[42:43]
+; GFX900-NEXT: v_cndmask_b32_e64 v30, 0, v30, s[42:43]
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: v_minimum_v16f64:
@@ -2410,107 +2410,107 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_min_f64 v[58:59], v[0:1], v[32:33]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[32:33]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[32:33]
; GFX950-NEXT: scratch_load_dword v33, off, s32 offset:112
; GFX950-NEXT: scratch_load_dword v32, off, s32 offset:108
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_min_f64 v[60:61], v[2:3], v[36:37]
-; GFX950-NEXT: v_cmp_u_f64_e64 s[0:1], v[2:3], v[36:37]
+; GFX950-NEXT: v_cmp_o_f64_e64 s[0:1], v[2:3], v[36:37]
; GFX950-NEXT: scratch_load_dword v37, off, s32 offset:120
; GFX950-NEXT: scratch_load_dword v36, off, s32 offset:116
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_min_f64 v[62:63], v[4:5], v[38:39]
-; GFX950-NEXT: v_cmp_u_f64_e64 s[2:3], v[4:5], v[38:39]
+; GFX950-NEXT: v_cmp_o_f64_e64 s[2:3], v[4:5], v[38:39]
; GFX950-NEXT: scratch_load_dword v39, off, s32 offset:128
; GFX950-NEXT: scratch_load_dword v38, off, s32 offset:124
; GFX950-NEXT: v_mov_b32_e32 v2, 0x7ff80000
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_min_f64 v[0:1], v[6:7], v[56:57]
-; GFX950-NEXT: v_cmp_u_f64_e64 s[4:5], v[6:7], v[56:57]
+; GFX950-NEXT: v_cmp_o_f64_e64 s[4:5], v[6:7], v[56:57]
; GFX950-NEXT: s_waitcnt vmcnt(23)
; GFX950-NEXT: v_min_f64 v[56:57], v[8:9], v[46:47]
-; GFX950-NEXT: v_cndmask_b32_e64 v58, v58, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v59, v59, v2, vcc
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[46:47]
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
-; GFX950-NEXT: v_cndmask_b32_e64 v7, v1, v2, s[4:5]
-; GFX950-NEXT: v_cndmask_b32_e64 v8, v56, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v9, v57, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v58, 0, v58, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v59, v2, v59, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[8:9], v[46:47]
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, v0, s[4:5]
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v2, v1, s[4:5]
+; GFX950-NEXT: v_cndmask_b32_e32 v8, 0, v56, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v9, v2, v57, vcc
; GFX950-NEXT: s_waitcnt vmcnt(21)
; GFX950-NEXT: v_min_f64 v[0:1], v[10:11], v[44:45]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[44:45]
-; GFX950-NEXT: v_cndmask_b32_e64 v60, v60, 0, s[0:1]
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v61, v2, s[0:1]
-; GFX950-NEXT: v_cndmask_b32_e64 v10, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v11, v1, v2, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[10:11], v[44:45]
+; GFX950-NEXT: v_cndmask_b32_e64 v60, 0, v60, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v2, v61, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v11, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(19)
; GFX950-NEXT: v_min_f64 v[0:1], v[12:13], v[42:43]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[42:43]
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v62, 0, s[2:3]
-; GFX950-NEXT: v_cndmask_b32_e64 v5, v63, v2, s[2:3]
-; GFX950-NEXT: v_cndmask_b32_e64 v12, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v13, v1, v2, vcc
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[12:13], v[42:43]
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, v62, s[2:3]
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v2, v63, s[2:3]
+; GFX950-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v13, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(17)
; GFX950-NEXT: v_min_f64 v[0:1], v[14:15], v[40:41]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[14:15], v[40:41]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[14:15], v[40:41]
; GFX950-NEXT: v_accvgpr_read_b32 v63, a15 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v62, a14 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v14, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v15, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v14, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v15, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(15)
; GFX950-NEXT: v_min_f64 v[0:1], v[16:17], v[54:55]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[16:17], v[54:55]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[16:17], v[54:55]
; GFX950-NEXT: v_accvgpr_read_b32 v61, a13 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v57, a9 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v16, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v17, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v16, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v17, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(13)
; GFX950-NEXT: v_min_f64 v[0:1], v[18:19], v[52:53]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[18:19], v[52:53]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[18:19], v[52:53]
; GFX950-NEXT: v_accvgpr_read_b32 v56, a8 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v47, a7 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v18, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v19, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v18, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v19, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(11)
; GFX950-NEXT: v_min_f64 v[0:1], v[20:21], v[50:51]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[20:21], v[50:51]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[20:21], v[50:51]
; GFX950-NEXT: v_accvgpr_read_b32 v46, a6 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v45, a5 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v20, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v21, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v20, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v21, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(9)
; GFX950-NEXT: v_min_f64 v[0:1], v[22:23], v[48:49]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[22:23], v[48:49]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[22:23], v[48:49]
; GFX950-NEXT: v_accvgpr_read_b32 v44, a4 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v43, a3 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v22, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v23, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v22, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v23, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(6)
; GFX950-NEXT: v_min_f64 v[0:1], v[24:25], v[34:35]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[24:25], v[34:35]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[24:25], v[34:35]
; GFX950-NEXT: v_accvgpr_read_b32 v42, a2 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse
-; GFX950-NEXT: v_cndmask_b32_e64 v24, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v25, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v24, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v25, v2, v1, vcc
; GFX950-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse
; GFX950-NEXT: s_waitcnt vmcnt(4)
; GFX950-NEXT: v_min_f64 v[0:1], v[26:27], v[32:33]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[26:27], v[32:33]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[26:27], v[32:33]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v26, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v27, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v26, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v27, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(2)
; GFX950-NEXT: v_min_f64 v[0:1], v[28:29], v[36:37]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[28:29], v[36:37]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[28:29], v[36:37]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v28, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v29, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v28, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v29, v2, v1, vcc
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_min_f64 v[0:1], v[30:31], v[38:39]
-; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[30:31], v[38:39]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[30:31], v[38:39]
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v30, v0, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e32 v31, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v30, 0, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v31, v2, v1, vcc
; GFX950-NEXT: v_mov_b32_e32 v0, v58
; GFX950-NEXT: v_mov_b32_e32 v1, v59
; GFX950-NEXT: v_mov_b32_e32 v2, v60
@@ -2551,10 +2551,10 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:104
; GFX10-NEXT: s_waitcnt vmcnt(24)
; GFX10-NEXT: v_min_f64 v[82:83], v[0:1], v[31:32]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[31:32]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[31:32]
; GFX10-NEXT: s_waitcnt vmcnt(22)
; GFX10-NEXT: v_min_f64 v[84:85], v[2:3], v[33:34]
-; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[33:34]
+; GFX10-NEXT: v_cmp_o_f64_e64 s4, v[2:3], v[33:34]
; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120
; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
@@ -2562,81 +2562,81 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108
; GFX10-NEXT: s_waitcnt vmcnt(24)
; GFX10-NEXT: v_min_f64 v[32:33], v[4:5], v[35:36]
-; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[4:5], v[35:36]
+; GFX10-NEXT: v_cmp_o_f64_e64 s5, v[4:5], v[35:36]
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128
; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
; GFX10-NEXT: s_waitcnt vmcnt(24)
; GFX10-NEXT: v_min_f64 v[34:35], v[6:7], v[48:49]
-; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[6:7], v[48:49]
+; GFX10-NEXT: v_cmp_o_f64_e64 s6, v[6:7], v[48:49]
; GFX10-NEXT: s_waitcnt vmcnt(21)
-; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[52:53]
+; GFX10-NEXT: v_cmp_o_f64_e64 s10, v[14:15], v[52:53]
; GFX10-NEXT: s_waitcnt vmcnt(19)
-; GFX10-NEXT: v_cmp_u_f64_e64 s9, v[12:13], v[54:55]
+; GFX10-NEXT: v_cmp_o_f64_e64 s9, v[12:13], v[54:55]
; GFX10-NEXT: s_waitcnt vmcnt(17)
-; GFX10-NEXT: v_cmp_u_f64_e64 s8, v[10:11], v[64:65]
+; GFX10-NEXT: v_cmp_o_f64_e64 s8, v[10:11], v[64:65]
; GFX10-NEXT: s_waitcnt vmcnt(16)
; GFX10-NEXT: v_min_f64 v[48:49], v[8:9], v[37:38]
-; GFX10-NEXT: v_cmp_u_f64_e64 s7, v[8:9], v[37:38]
+; GFX10-NEXT: v_cmp_o_f64_e64 s7, v[8:9], v[37:38]
; GFX10-NEXT: v_min_f64 v[36:37], v[10:11], v[64:65]
; GFX10-NEXT: v_min_f64 v[38:39], v[12:13], v[54:55]
; GFX10-NEXT: v_min_f64 v[54:55], v[14:15], v[52:53]
; GFX10-NEXT: s_waitcnt vmcnt(11)
; GFX10-NEXT: v_min_f64 v[64:65], v[20:21], v[70:71]
-; GFX10-NEXT: v_cmp_u_f64_e64 s13, v[20:21], v[70:71]
+; GFX10-NEXT: v_cmp_o_f64_e64 s13, v[20:21], v[70:71]
; GFX10-NEXT: s_waitcnt vmcnt(9)
-; GFX10-NEXT: v_cmp_u_f64_e64 s12, v[18:19], v[80:81]
+; GFX10-NEXT: v_cmp_o_f64_e64 s12, v[18:19], v[80:81]
; GFX10-NEXT: s_waitcnt vmcnt(8)
; GFX10-NEXT: v_min_f64 v[52:53], v[16:17], v[50:51]
-; GFX10-NEXT: v_cmp_u_f64_e64 s11, v[16:17], v[50:51]
+; GFX10-NEXT: v_cmp_o_f64_e64 s11, v[16:17], v[50:51]
; GFX10-NEXT: v_min_f64 v[50:51], v[18:19], v[80:81]
; GFX10-NEXT: v_min_f64 v[70:71], v[22:23], v[68:69]
-; GFX10-NEXT: v_cmp_u_f64_e64 s14, v[22:23], v[68:69]
+; GFX10-NEXT: v_cmp_o_f64_e64 s14, v[22:23], v[68:69]
; GFX10-NEXT: s_waitcnt vmcnt(7)
; GFX10-NEXT: v_min_f64 v[68:69], v[24:25], v[66:67]
-; GFX10-NEXT: v_cmp_u_f64_e64 s15, v[24:25], v[66:67]
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v34, 0, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v35, 0x7ff80000, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v48, 0, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v49, 0x7ff80000, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v36, 0, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v37, 0x7ff80000, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v38, 0, s9
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v39, 0x7ff80000, s9
-; GFX10-NEXT: v_cndmask_b32_e64 v14, v54, 0, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v55, 0x7ff80000, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v16, v52, 0, s11
-; GFX10-NEXT: v_cndmask_b32_e64 v17, v53, 0x7ff80000, s11
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v50, 0, s12
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v51, 0x7ff80000, s12
-; GFX10-NEXT: v_cndmask_b32_e64 v20, v64, 0, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v21, v65, 0x7ff80000, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v70, 0, s14
-; GFX10-NEXT: v_cndmask_b32_e64 v23, v71, 0x7ff80000, s14
-; GFX10-NEXT: v_cndmask_b32_e64 v24, v68, 0, s15
-; GFX10-NEXT: v_cndmask_b32_e64 v25, v69, 0x7ff80000, s15
+; GFX10-NEXT: v_cmp_o_f64_e64 s15, v[24:25], v[66:67]
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v34, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v35, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v48, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0x7ff80000, v49, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v36, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0x7ff80000, v37, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, v38, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v13, 0x7ff80000, v39, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, v54, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v15, 0x7ff80000, v55, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, v52, s11
+; GFX10-NEXT: v_cndmask_b32_e64 v17, 0x7ff80000, v53, s11
+; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, v50, s12
+; GFX10-NEXT: v_cndmask_b32_e64 v19, 0x7ff80000, v51, s12
+; GFX10-NEXT: v_cndmask_b32_e64 v20, 0, v64, s13
+; GFX10-NEXT: v_cndmask_b32_e64 v21, 0x7ff80000, v65, s13
+; GFX10-NEXT: v_cndmask_b32_e64 v22, 0, v70, s14
+; GFX10-NEXT: v_cndmask_b32_e64 v23, 0x7ff80000, v71, s14
+; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, v68, s15
+; GFX10-NEXT: v_cndmask_b32_e64 v25, 0x7ff80000, v69, s15
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_min_f64 v[80:81], v[28:29], v[0:1]
-; GFX10-NEXT: v_cmp_u_f64_e64 s17, v[28:29], v[0:1]
+; GFX10-NEXT: v_cmp_o_f64_e64 s17, v[28:29], v[0:1]
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_min_f64 v[66:67], v[26:27], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e64 s16, v[26:27], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v82, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e64 s16, v[26:27], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v82, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_min_f64 v[86:87], v[30:31], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e64 s18, v[30:31], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v83, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v84, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v85, 0x7ff80000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v32, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v33, 0x7ff80000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v28, v80, 0, s17
-; GFX10-NEXT: v_cndmask_b32_e64 v29, v81, 0x7ff80000, s17
-; GFX10-NEXT: v_cndmask_b32_e64 v26, v66, 0, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v27, v67, 0x7ff80000, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v30, v86, 0, s18
-; GFX10-NEXT: v_cndmask_b32_e64 v31, v87, 0x7ff80000, s18
+; GFX10-NEXT: v_cmp_o_f64_e64 s18, v[30:31], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v83, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v84, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v85, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, v32, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v33, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v28, 0, v80, s17
+; GFX10-NEXT: v_cndmask_b32_e64 v29, 0x7ff80000, v81, s17
+; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, v66, s16
+; GFX10-NEXT: v_cndmask_b32_e64 v27, 0x7ff80000, v67, s16
+; GFX10-NEXT: v_cndmask_b32_e64 v30, 0, v86, s18
+; GFX10-NEXT: v_cndmask_b32_e64 v31, 0x7ff80000, v87, s18
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minimum_v16f64:
@@ -2678,84 +2678,84 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:124
; GFX11-NEXT: s_waitcnt vmcnt(30)
; GFX11-NEXT: v_min_f64 v[96:97], v[0:1], v[32:33]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[32:33]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[32:33]
; GFX11-NEXT: s_waitcnt vmcnt(28)
; GFX11-NEXT: v_min_f64 v[32:33], v[2:3], v[34:35]
-; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[34:35]
+; GFX11-NEXT: v_cmp_o_f64_e64 s0, v[2:3], v[34:35]
; GFX11-NEXT: s_waitcnt vmcnt(26)
; GFX11-NEXT: v_min_f64 v[34:35], v[4:5], v[36:37]
-; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[4:5], v[36:37]
+; GFX11-NEXT: v_cmp_o_f64_e64 s1, v[4:5], v[36:37]
; GFX11-NEXT: s_waitcnt vmcnt(24)
; GFX11-NEXT: v_min_f64 v[36:37], v[6:7], v[38:39]
-; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[6:7], v[38:39]
+; GFX11-NEXT: v_cmp_o_f64_e64 s2, v[6:7], v[38:39]
; GFX11-NEXT: s_waitcnt vmcnt(22)
; GFX11-NEXT: v_min_f64 v[38:39], v[8:9], v[48:49]
-; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[8:9], v[48:49]
+; GFX11-NEXT: v_cmp_o_f64_e64 s3, v[8:9], v[48:49]
; GFX11-NEXT: s_waitcnt vmcnt(20)
; GFX11-NEXT: v_min_f64 v[48:49], v[10:11], v[50:51]
-; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[10:11], v[50:51]
+; GFX11-NEXT: v_cmp_o_f64_e64 s4, v[10:11], v[50:51]
; GFX11-NEXT: s_waitcnt vmcnt(18)
; GFX11-NEXT: v_min_f64 v[50:51], v[12:13], v[52:53]
-; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[52:53]
+; GFX11-NEXT: v_cmp_o_f64_e64 s5, v[12:13], v[52:53]
; GFX11-NEXT: s_waitcnt vmcnt(16)
; GFX11-NEXT: v_min_f64 v[52:53], v[14:15], v[54:55]
-; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[54:55]
+; GFX11-NEXT: v_cmp_o_f64_e64 s6, v[14:15], v[54:55]
; GFX11-NEXT: s_waitcnt vmcnt(14)
; GFX11-NEXT: v_min_f64 v[54:55], v[16:17], v[64:65]
-; GFX11-NEXT: v_cmp_u_f64_e64 s7, v[16:17], v[64:65]
+; GFX11-NEXT: v_cmp_o_f64_e64 s7, v[16:17], v[64:65]
; GFX11-NEXT: s_waitcnt vmcnt(12)
; GFX11-NEXT: v_min_f64 v[64:65], v[18:19], v[66:67]
-; GFX11-NEXT: v_cmp_u_f64_e64 s8, v[18:19], v[66:67]
+; GFX11-NEXT: v_cmp_o_f64_e64 s8, v[18:19], v[66:67]
; GFX11-NEXT: s_waitcnt vmcnt(10)
; GFX11-NEXT: v_min_f64 v[66:67], v[20:21], v[68:69]
-; GFX11-NEXT: v_cmp_u_f64_e64 s9, v[20:21], v[68:69]
+; GFX11-NEXT: v_cmp_o_f64_e64 s9, v[20:21], v[68:69]
; GFX11-NEXT: s_waitcnt vmcnt(8)
; GFX11-NEXT: v_min_f64 v[68:69], v[22:23], v[70:71]
-; GFX11-NEXT: v_cmp_u_f64_e64 s10, v[22:23], v[70:71]
+; GFX11-NEXT: v_cmp_o_f64_e64 s10, v[22:23], v[70:71]
; GFX11-NEXT: s_waitcnt vmcnt(6)
; GFX11-NEXT: v_min_f64 v[70:71], v[24:25], v[80:81]
-; GFX11-NEXT: v_cmp_u_f64_e64 s11, v[24:25], v[80:81]
+; GFX11-NEXT: v_cmp_o_f64_e64 s11, v[24:25], v[80:81]
; GFX11-NEXT: s_waitcnt vmcnt(4)
; GFX11-NEXT: v_min_f64 v[80:81], v[26:27], v[82:83]
-; GFX11-NEXT: v_cmp_u_f64_e64 s12, v[26:27], v[82:83]
+; GFX11-NEXT: v_cmp_o_f64_e64 s12, v[26:27], v[82:83]
; GFX11-NEXT: s_waitcnt vmcnt(2)
; GFX11-NEXT: v_min_f64 v[82:83], v[28:29], v[84:85]
-; GFX11-NEXT: v_cmp_u_f64_e64 s13, v[28:29], v[84:85]
+; GFX11-NEXT: v_cmp_o_f64_e64 s13, v[28:29], v[84:85]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_min_f64 v[84:85], v[30:31], v[86:87]
-; GFX11-NEXT: v_cmp_u_f64_e64 s14, v[30:31], v[86:87]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v96, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v97, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v32, 0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v33, 0x7ff80000, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v34, 0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v35, 0x7ff80000, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v36, 0, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v37, 0x7ff80000, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v38, 0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v39, 0x7ff80000, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v48, 0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v11, v49, 0x7ff80000, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v50, 0, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v13, v51, 0x7ff80000, s5
-; GFX11-NEXT: v_cndmask_b32_e64 v14, v52, 0, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v15, v53, 0x7ff80000, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v16, v54, 0, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v17, v55, 0x7ff80000, s7
-; GFX11-NEXT: v_cndmask_b32_e64 v18, v64, 0, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v19, v65, 0x7ff80000, s8
-; GFX11-NEXT: v_cndmask_b32_e64 v20, v66, 0, s9
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v67, 0x7ff80000, s9
-; GFX11-NEXT: v_cndmask_b32_e64 v22, v68, 0, s10
-; GFX11-NEXT: v_cndmask_b32_e64 v23, v69, 0x7ff80000, s10
-; GFX11-NEXT: v_cndmask_b32_e64 v24, v70, 0, s11
-; GFX11-NEXT: v_cndmask_b32_e64 v25, v71, 0x7ff80000, s11
-; GFX11-NEXT: v_cndmask_b32_e64 v26, v80, 0, s12
-; GFX11-NEXT: v_cndmask_b32_e64 v27, v81, 0x7ff80000, s12
-; GFX11-NEXT: v_cndmask_b32_e64 v28, v82, 0, s13
-; GFX11-NEXT: v_cndmask_b32_e64 v29, v83, 0x7ff80000, s13
-; GFX11-NEXT: v_cndmask_b32_e64 v30, v84, 0, s14
-; GFX11-NEXT: v_cndmask_b32_e64 v31, v85, 0x7ff80000, s14
+; GFX11-NEXT: v_cmp_o_f64_e64 s14, v[30:31], v[86:87]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v96, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v97, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v32, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0x7ff80000, v33, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, v34, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x7ff80000, v35, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v36, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0x7ff80000, v37, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v38, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0x7ff80000, v39, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v48, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v11, 0x7ff80000, v49, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, v50, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v13, 0x7ff80000, v51, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v14, 0, v52, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v15, 0x7ff80000, v53, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v16, 0, v54, s7
+; GFX11-NEXT: v_cndmask_b32_e64 v17, 0x7ff80000, v55, s7
+; GFX11-NEXT: v_cndmask_b32_e64 v18, 0, v64, s8
+; GFX11-NEXT: v_cndmask_b32_e64 v19, 0x7ff80000, v65, s8
+; GFX11-NEXT: v_cndmask_b32_e64 v20, 0, v66, s9
+; GFX11-NEXT: v_cndmask_b32_e64 v21, 0x7ff80000, v67, s9
+; GFX11-NEXT: v_cndmask_b32_e64 v22, 0, v68, s10
+; GFX11-NEXT: v_cndmask_b32_e64 v23, 0x7ff80000, v69, s10
+; GFX11-NEXT: v_cndmask_b32_e64 v24, 0, v70, s11
+; GFX11-NEXT: v_cndmask_b32_e64 v25, 0x7ff80000, v71, s11
+; GFX11-NEXT: v_cndmask_b32_e64 v26, 0, v80, s12
+; GFX11-NEXT: v_cndmask_b32_e64 v27, 0x7ff80000, v81, s12
+; GFX11-NEXT: v_cndmask_b32_e64 v28, 0, v82, s13
+; GFX11-NEXT: v_cndmask_b32_e64 v29, 0x7ff80000, v83, s13
+; GFX11-NEXT: v_cndmask_b32_e64 v30, 0, v84, s14
+; GFX11-NEXT: v_cndmask_b32_e64 v31, 0x7ff80000, v85, s14
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_minimum_v16f64:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
index af914bd4043cf..696832ddc6d27 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
@@ -87,10 +87,11 @@ define amdgpu_kernel void @v_round_f64(ptr addrspace(1) %out, ptr addrspace(1) %
; SI-NEXT: v_not_b32_e32 v5, v5
; SI-NEXT: v_not_b32_e32 v4, v4
; SI-NEXT: v_and_b32_e32 v5, v3, v5
-; SI-NEXT: v_and_b32_e32 v4, v2, v4
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v6
+; SI-NEXT: v_and_b32_e32 v4, v2, v4
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, -1, v6
+; SI-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v6
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll b/llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll
index 12ccdfff07c6f..1703dd8ace0dc 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll
@@ -40,9 +40,8 @@ define amdgpu_cs void @test_i32_sle(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_i32_sgt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_i32_sgt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 2, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -58,9 +57,8 @@ define amdgpu_cs void @test_i32_sgt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_i32_slt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_i32_slt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 2, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 3, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -113,11 +111,9 @@ define amdgpu_cs void @test_i64_sle(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_i64_sgt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_i64_sgt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_gt_i64_e32 vcc_lo, 2, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_lt_i64_e32 vcc_lo, 1, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -133,11 +129,9 @@ define amdgpu_cs void @test_i64_sgt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_i64_slt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_i64_slt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_lt_i64_e32 vcc_lo, 2, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_gt_i64_e32 vcc_lo, 3, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -154,9 +148,8 @@ define amdgpu_cs void @test_i64_slt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_u32_eq(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_u32_eq:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 1, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -191,10 +184,12 @@ define amdgpu_cs void @test_mixed(i32 %a, i32 %p, i32 %q, i32 %r, i32 %s, ptr ad
; GCN-LABEL: test_mixed:
; GCN: ; %bb.0: ; %.entry
; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, -1, v0
+; GCN-NEXT: v_cmp_ne_u32_e64 s0, -1, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v4, 0, vcc_lo
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, v3, s0
+; GCN-NEXT: v_cndmask_b32_e64 v3, 0, v4, s0
; GCN-NEXT: global_store_b128 v[5:6], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -235,9 +230,8 @@ define amdgpu_cs void @test_sgpr(i32 %a, i32 %p, i32 inreg %q, i32 inreg %r, ptr
define amdgpu_cs void @test_u32_ne(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_u32_ne:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 1, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -287,9 +281,8 @@ define amdgpu_cs void @test_u32_ule(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_u32_ugt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_u32_ugt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 2, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 1, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -305,9 +298,8 @@ define amdgpu_cs void @test_u32_ugt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_u32_ult(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_u32_ult:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 2, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 3, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -324,11 +316,9 @@ define amdgpu_cs void @test_u32_ult(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_u64_eq(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_u64_eq:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, 1, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_ne_u64_e32 vcc_lo, 1, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -344,11 +334,9 @@ define amdgpu_cs void @test_u64_eq(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out
define amdgpu_cs void @test_u64_ne(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_u64_ne:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_ne_u64_e32 vcc_lo, 1, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, 1, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -400,11 +388,9 @@ define amdgpu_cs void @test_u64_ule(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_u64_ugt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_u64_ugt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_gt_u64_e32 vcc_lo, 2, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -420,11 +406,9 @@ define amdgpu_cs void @test_u64_ugt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_u64_ult(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_u64_ult:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_lt_u64_e32 vcc_lo, 2, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_gt_u64_e32 vcc_lo, 3, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -441,9 +425,8 @@ define amdgpu_cs void @test_u64_ult(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %ou
define amdgpu_cs void @test_f32_oeq(float %a, float %p, float %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f32_oeq:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_eq_f32_e32 vcc_lo, 2.0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_neq_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -479,9 +462,8 @@ define amdgpu_cs void @test_f32_negative_modifiers(float %a, float %p, float %q,
define amdgpu_cs void @test_f32_one(float %a, float %p, float %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f32_one:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_lg_f32_e32 vcc_lo, 2.0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -497,9 +479,8 @@ define amdgpu_cs void @test_f32_one(float %a, float %p, float %q, ptr addrspace(
define amdgpu_cs void @test_f32_ord(float %a, float %p, float %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f32_ord:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -515,9 +496,8 @@ define amdgpu_cs void @test_f32_ord(float %a, float %p, float %q, ptr addrspace(
define amdgpu_cs void @test_f32_uno(float %a, float %p, float %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f32_uno:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -533,9 +513,8 @@ define amdgpu_cs void @test_f32_uno(float %a, float %p, float %q, ptr addrspace(
define amdgpu_cs void @test_f32_oge(float %a, float %p, float %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f32_oge:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, 2.0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_nge_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -551,9 +530,8 @@ define amdgpu_cs void @test_f32_oge(float %a, float %p, float %q, ptr addrspace(
define amdgpu_cs void @test_f32_ole(float %a, float %p, float %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f32_ole:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, 2.0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_nle_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -569,9 +547,8 @@ define amdgpu_cs void @test_f32_ole(float %a, float %p, float %q, ptr addrspace(
define amdgpu_cs void @test_f32_ogt(float %a, float %p, float %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f32_ogt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, 2.0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -587,9 +564,8 @@ define amdgpu_cs void @test_f32_ogt(float %a, float %p, float %q, ptr addrspace(
define amdgpu_cs void @test_f32_olt(float %a, float %p, float %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f32_olt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
; GCN-NEXT: s_endpgm
.entry:
@@ -606,11 +582,9 @@ define amdgpu_cs void @test_f32_olt(float %a, float %p, float %q, ptr addrspace(
define amdgpu_cs void @test_f64_oeq(double %a, double %p, double %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f64_oeq:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_eq_f64_e32 vcc_lo, 2.0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_neq_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -626,11 +600,9 @@ define amdgpu_cs void @test_f64_oeq(double %a, double %p, double %q, ptr addrspa
define amdgpu_cs void @test_f64_one(double %a, double %p, double %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f64_one:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_lg_f64_e32 vcc_lo, 2.0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -646,11 +618,9 @@ define amdgpu_cs void @test_f64_one(double %a, double %p, double %q, ptr addrspa
define amdgpu_cs void @test_f64_oge(double %a, double %p, double %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f64_oge:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_ge_f64_e32 vcc_lo, 2.0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_nge_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -666,11 +636,9 @@ define amdgpu_cs void @test_f64_oge(double %a, double %p, double %q, ptr addrspa
define amdgpu_cs void @test_f64_ole(double %a, double %p, double %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f64_ole:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, 2.0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_nle_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -686,11 +654,9 @@ define amdgpu_cs void @test_f64_ole(double %a, double %p, double %q, ptr addrspa
define amdgpu_cs void @test_f64_ogt(double %a, double %p, double %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f64_ogt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, 2.0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_ngt_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -706,11 +672,9 @@ define amdgpu_cs void @test_f64_ogt(double %a, double %p, double %q, ptr addrspa
define amdgpu_cs void @test_f64_olt(double %a, double %p, double %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f64_olt:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, 2.0, v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_nlt_f64_e32 vcc_lo, 2.0, v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -726,11 +690,9 @@ define amdgpu_cs void @test_f64_olt(double %a, double %p, double %q, ptr addrspa
define amdgpu_cs void @test_f64_ord(double %a, double %p, double %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f64_ord:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
@@ -746,11 +708,9 @@ define amdgpu_cs void @test_f64_ord(double %a, double %p, double %q, ptr addrspa
define amdgpu_cs void @test_f64_uno(double %a, double %p, double %q, ptr addrspace(1) %out) {
; GCN-LABEL: test_f64_uno:
; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v3, v5, 0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GCN-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
+; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
; GCN-NEXT: s_endpgm
.entry:
diff --git a/llvm/test/CodeGen/AMDGPU/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/uaddsat.ll
index 79adc9ead62e1..867ad96fd5ed0 100644
--- a/llvm/test/CodeGen/AMDGPU/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/uaddsat.ll
@@ -696,9 +696,9 @@ define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
+; GFX6-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, -1, v3, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_uaddsat_i64:
@@ -706,9 +706,9 @@ define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
+; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[0:1]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, -1, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_i64:
@@ -716,9 +716,9 @@ define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, -1, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_i64:
@@ -726,9 +726,9 @@ define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc_lo
+; GFX10-NEXT: v_cmp_ge_u64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, -1, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_uaddsat_i64:
@@ -737,9 +737,8 @@ define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo
-; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc_lo
+; GFX11-NEXT: v_cmp_ge_u64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX11-NEXT: v_dual_cndmask_b32 v0, -1, v2 :: v_dual_cndmask_b32 v1, -1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
diff --git a/llvm/test/CodeGen/AMDGPU/usubsat.ll b/llvm/test/CodeGen/AMDGPU/usubsat.ll
index 90491a07289a0..9e2d1eac3277c 100644
--- a/llvm/test/CodeGen/AMDGPU/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/usubsat.ll
@@ -732,9 +732,9 @@ define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
-; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
+; GFX6-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_usubsat_i64:
@@ -742,9 +742,9 @@ define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v2
; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
-; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
+; GFX8-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_i64:
@@ -752,9 +752,9 @@ define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
-; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
+; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_i64:
@@ -762,9 +762,9 @@ define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, v2
; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GFX10-NEXT: v_cmp_le_u64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_usubsat_i64:
@@ -772,9 +772,8 @@ define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v0, v2
; GFX11-NEXT: v_sub_co_ci_u32_e64 v3, null, v1, v3, vcc_lo
-; GFX11-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GFX11-NEXT: v_cmp_le_u64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX11-NEXT: v_dual_cndmask_b32 v0, 0, v2 :: v_dual_cndmask_b32 v1, 0, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
diff --git a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
index a41063f467d01..1ef4164a93b9f 100644
--- a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
@@ -2043,9 +2043,9 @@ define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2(ptr add
; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[2:3], s[10:11]
-; SI-NEXT: v_cmp_nle_f32_e32 vcc, 4.0, v2
-; SI-NEXT: v_cndmask_b32_e64 v2, v3, -1.0, vcc
-; SI-NEXT: v_cndmask_b32_e64 v3, v3, -2.0, vcc
+; SI-NEXT: v_cmp_le_f32_e32 vcc, 4.0, v2
+; SI-NEXT: v_cndmask_b32_e32 v2, -1.0, v3, vcc
+; SI-NEXT: v_cndmask_b32_e32 v3, -2.0, v3, vcc
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64
@@ -2071,9 +2071,9 @@ define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2(ptr add
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_cmp_nle_f32_e32 vcc, 4.0, v5
-; VI-NEXT: v_cndmask_b32_e64 v3, v2, -1.0, vcc
-; VI-NEXT: v_cndmask_b32_e64 v2, v2, -2.0, vcc
+; VI-NEXT: v_cmp_le_f32_e32 vcc, 4.0, v5
+; VI-NEXT: v_cndmask_b32_e32 v3, -1.0, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v2, -2.0, v2, vcc
; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dword v[0:1], v2
@@ -2091,9 +2091,9 @@ define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2(ptr add
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v2, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_nle_f32_e32 vcc, 4.0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, -1.0, vcc
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, -2.0, vcc
+; GFX10-NEXT: v_cmp_le_f32_e32 vcc, 4.0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v1, -1.0, v2, vcc
+; GFX10-NEXT: v_cndmask_b32_e32 v2, -2.0, v2, vcc
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v0, v2, s[0:1]
@@ -2113,9 +2113,9 @@ define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2(ptr add
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: global_load_b32 v2, v0, s[4:5] glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_nle_f32_e32 vcc, 4.0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, -1.0, vcc
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, -2.0, vcc
+; GFX11-NEXT: v_cmp_le_f32_e32 vcc, 4.0, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, -1.0, v2, vcc
+; GFX11-NEXT: v_cndmask_b32_e32 v2, -2.0, v2, vcc
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b32 v0, v2, s[0:1] dlc
@@ -2135,9 +2135,9 @@ define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2(ptr add
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_nle_f32_e32 vcc, 4.0, v1
-; GFX12-NEXT: v_cndmask_b32_e64 v1, v2, -1.0, vcc
-; GFX12-NEXT: v_cndmask_b32_e64 v2, v2, -2.0, vcc
+; GFX12-NEXT: v_cmp_le_f32_e32 vcc, 4.0, v1
+; GFX12-NEXT: v_cndmask_b32_e32 v1, -1.0, v2, vcc
+; GFX12-NEXT: v_cndmask_b32_e32 v2, -2.0, v2, vcc
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_store_b32 v0, v2, s[0:1] scope:SCOPE_SYS
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
index 41fad10051dac..6c71ae5c4d0e8 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
@@ -1729,50 +1729,50 @@ define double @test_vector_reduce_fmaximum_v2double(<2 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v2double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v2double:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v2double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v2double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v2double:
@@ -1794,28 +1794,28 @@ define double @test_vector_reduce_fmaximum_v3double(<3 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v3double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v3double:
@@ -1823,44 +1823,44 @@ define double @test_vector_reduce_fmaximum_v3double(<3 x double> %v) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v3double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v7, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v3double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v7, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v7, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v3double:
@@ -1884,36 +1884,36 @@ define double @test_vector_reduce_fmaximum_v4double(<4 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v4double:
@@ -1921,58 +1921,58 @@ define double @test_vector_reduce_fmaximum_v4double(<4 x double> %v) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v4double:
@@ -1997,68 +1997,68 @@ define double @test_vector_reduce_fmaximum_v8double(<8 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v8double:
@@ -2066,116 +2066,116 @@ define double @test_vector_reduce_fmaximum_v8double(<8 x double> %v) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v8double:
@@ -2206,136 +2206,136 @@ define double @test_vector_reduce_fmaximum_v16double(<16 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v31, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[18:19]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[20:21]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[22:23]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[24:25]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[26:27]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[28:29]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[30:31]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v31, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[18:19]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[20:21]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[22:23]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[24:25]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[26:27]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[28:29]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[30:31]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v16double:
@@ -2344,237 +2344,237 @@ define double @test_vector_reduce_fmaximum_v16double(<16 x double> %v) {
; GFX9-NEXT: scratch_load_dword v31, off, s32
; GFX9-NEXT: v_max_f64 v[32:33], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v34, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v33, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[18:19]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[20:21]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[22:23]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[24:25]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[26:27]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[28:29]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[30:31]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v32, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v32, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v31, vcc_lo
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[16:17]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[18:19]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[18:19]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[20:21]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[20:21]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[22:23]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[22:23]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[24:25]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[24:25]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[26:27]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[26:27]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[28:29]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[28:29]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[30:31]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[30:31]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v32, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v32, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v31, vcc_lo
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[12:13]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[18:19]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[18:19]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[20:21]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[20:21]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[22:23]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[22:23]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[24:25]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[24:25]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[26:27]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[26:27]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[28:29]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[28:29]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[30:31]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[30:31]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v16double:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 61819a85dd82c..c36400fb65988 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -1978,50 +1978,50 @@ define double @test_vector_reduce_fminimum_v2double(<2 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v2double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v2double:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v2double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v2double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fminimum_v2double:
@@ -2043,28 +2043,28 @@ define double @test_vector_reduce_fminimum_v3double(<3 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v3double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v3double:
@@ -2072,44 +2072,44 @@ define double @test_vector_reduce_fminimum_v3double(<3 x double> %v) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v3double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v7, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v3double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v7, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v7, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fminimum_v3double:
@@ -2133,36 +2133,36 @@ define double @test_vector_reduce_fminimum_v4double(<4 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v4double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v4double:
@@ -2170,58 +2170,58 @@ define double @test_vector_reduce_fminimum_v4double(<4 x double> %v) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v4double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v4double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v4double:
@@ -2259,68 +2259,68 @@ define double @test_vector_reduce_fminimum_v8double(<8 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v8double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v8double:
@@ -2328,116 +2328,116 @@ define double @test_vector_reduce_fminimum_v8double(<8 x double> %v) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v8double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v8double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v17, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v8double:
@@ -2486,136 +2486,136 @@ define double @test_vector_reduce_fminimum_v16double(<16 x double> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v31, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[18:19]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[20:21]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[22:23]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[24:25]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[26:27]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[28:29]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
+; GFX7-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[30:31]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v16double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v31, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[18:19]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[20:21]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[22:23]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[24:25]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[26:27]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[28:29]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
+; GFX8-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[30:31]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v33, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v16double:
@@ -2624,237 +2624,237 @@ define double @test_vector_reduce_fminimum_v16double(<16 x double> %v) {
; GFX9-NEXT: scratch_load_dword v31, off, s32
; GFX9-NEXT: v_min_f64 v[32:33], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v34, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v33, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v32, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[6:7]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[10:11]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[12:13]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[14:15]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[16:17]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[18:19]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[20:21]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[22:23]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[24:25]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[26:27]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[28:29]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[30:31]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v34, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v16double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v32, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v32, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v31, vcc_lo
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[12:13]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[16:17]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[18:19]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[18:19]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[20:21]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[20:21]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[22:23]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[22:23]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[24:25]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[24:25]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[26:27]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[26:27]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[28:29]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[28:29]
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[30:31]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[30:31]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v16double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v32, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v32, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v31, vcc_lo
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[12:13]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[18:19]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[18:19]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[20:21]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[20:21]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[22:23]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[22:23]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[24:25]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[24:25]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[26:27]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[26:27]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[28:29]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[28:29]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[30:31]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[30:31]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v16double:
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