[llvm] [DAG] canCreateUndefOrPoison – mark fneg/fadd/fsub/fmul/fdiv/frem as not poison generating (PR #142345)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 2 02:59:38 PDT 2025
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/142345
>From 3cc4a4c5ab260a9bd718ade51fc1495954c16597 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Sun, 1 Jun 2025 14:08:43 +0000
Subject: [PATCH 1/4] =?UTF-8?q?[DAG]=20canCreateUndefOrPoison=20=E2=80=93?=
=?UTF-8?q?=20mark=20fneg/fadd/fsub/fmul/fdiv/frem=20as=20not=20poison=20g?=
=?UTF-8?q?enerating?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 +
llvm/test/CodeGen/AMDGPU/freeze-binary.ll | 282 ++++++++++++++++++
2 files changed, 288 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/freeze-binary.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1506bc4ee187d..279c7daf71c33 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5579,6 +5579,12 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
+ case ISD::FNEG:
+ case ISD::FADD:
+ case ISD::FSUB:
+ case ISD::FMUL:
+ case ISD::FDIV:
+ case ISD::FREM:
// No poison except from flags (which is handled above)
return false;
diff --git a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
new file mode 100644
index 0000000000000..4321cedcc8b96
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
@@ -0,0 +1,282 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX11
+define float @freeze_fadd(float %input) nounwind {
+; GFX11-LABEL: freeze_fadd:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v0, 2.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
+ %y = freeze float %x
+ %z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
+ ret float %z
+}
+
+define float @freeze_fadd_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_fadd_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fadd nnan contract float %input, 1.000000e+00
+ %y = freeze float %x
+ %z = fadd nnan contract float %y, 1.000000e+00
+ ret float %z
+}
+
+define <4 x float> @freeze_fadd_vec(<4 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fadd_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
+; GFX11-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fadd reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ %y = freeze <4 x float> %x
+ %z = fadd reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ ret <4 x float> %z
+}
+
+define float @freeze_fsub(float %input) nounwind {
+; GFX11-LABEL: freeze_fsub:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fsub reassoc nsz arcp contract afn float %input, 1.000000e+00
+ %y = freeze float %x
+ %z = fsub reassoc nsz arcp contract afn float %y, 1.000000e+00
+ ret float %z
+}
+
+define float @freeze_fsub_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_fsub_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fsub nnan contract float %input, 1.000000e+00
+ %y = freeze float %x
+ %z = fsub nnan contract float %y, 1.000000e+00
+ ret float %z
+}
+
+define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fsub_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
+; GFX11-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fsub reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ %y = freeze <4 x float> %x
+ %z = fsub reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ ret <4 x float> %z
+}
+
+define float @freeze_fmul(float %input) nounwind {
+; GFX11-LABEL: freeze_fmul:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 4.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fmul reassoc nsz arcp contract afn float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = fmul reassoc nsz arcp contract afn float %y, 2.000000e+00
+ ret float %z
+}
+
+define float @freeze_fmul_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_fmul_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fmul nnan contract float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = fmul nnan contract float %y, 2.000000e+00
+ ret float %z
+}
+
+define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fmul_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
+; GFX11-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
+; GFX11-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
+; GFX11-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fmul reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ %y = freeze <8 x float> %x
+ %z = fmul reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ ret <8 x float> %z
+}
+
+define float @freeze_fdiv(float %input) nounwind {
+; GFX11-LABEL: freeze_fdiv:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fdiv reassoc nsz arcp contract afn float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = fdiv reassoc nsz arcp contract afn float %y, 2.000000e+00
+ ret float %z
+}
+
+define float @freeze_fdiv_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_fdiv_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fdiv nnan contract float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = fdiv nnan contract float %y, 2.000000e+00
+ ret float %z
+}
+
+define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fdiv_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
+; GFX11-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
+; GFX11-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
+; GFX11-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fdiv reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ %y = freeze <8 x float> %x
+ %z = fdiv reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ ret <8 x float> %z
+}
+
+define float @freeze_frem(float %input) nounwind {
+; GFX11-LABEL: freeze_frem:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v1, v1
+; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = frem reassoc nsz arcp contract afn float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = frem reassoc nsz arcp contract afn float %y, 2.000000e+00
+ ret float %z
+}
+
+define float @freeze_frem_nnan(float %input) nounwind {
+; GFX11-LABEL: freeze_frem_nnan:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v1, v1
+; GFX11-NEXT: v_fma_f32 v1, -2.0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v2, v2
+; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = frem nnan contract float %input, 2.000000e+00
+ %y = freeze float %x
+ %z = frem nnan contract float %y, 2.000000e+00
+ ret float %z
+}
+
+define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
+; GFX11-LABEL: freeze_frem_vec:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
+; GFX11-NEXT: v_trunc_f32_e32 v11, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_trunc_f32_e32 v8, v8
+; GFX11-NEXT: v_trunc_f32_e32 v9, v9
+; GFX11-NEXT: v_mul_f32_e32 v10, 0.5, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
+; GFX11-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v10, v10
+; GFX11-NEXT: v_trunc_f32_e32 v9, v7
+; GFX11-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
+; GFX11-NEXT: v_mul_f32_e32 v8, 0.5, v1
+; GFX11-NEXT: v_trunc_f32_e32 v9, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
+; GFX11-NEXT: v_trunc_f32_e32 v8, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v8
+; GFX11-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
+; GFX11-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
+; GFX11-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_trunc_f32_e32 v8, v10
+; GFX11-NEXT: v_trunc_f32_e32 v10, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
+; GFX11-NEXT: v_trunc_f32_e32 v8, v11
+; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
+; GFX11-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_fmac_f32_e32 v7, -4.0, v8
+; GFX11-NEXT: v_trunc_f32_e32 v9, v12
+; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
+; GFX11-NEXT: v_trunc_f32_e32 v9, v11
+; GFX11-NEXT: v_trunc_f32_e32 v11, v3
+; GFX11-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_trunc_f32_e32 v8, v10
+; GFX11-NEXT: v_trunc_f32_e32 v10, v12
+; GFX11-NEXT: v_trunc_f32_e32 v12, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_fmac_f32_e32 v2, -2.0, v8
+; GFX11-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_sub_f32_e32 v4, v4, v12
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = frem reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+ %y = freeze <8 x float> %x
+ %z = frem reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+ ret <8 x float> %z
+}
>From 66f6e1b435ac95f91104bd02cec62f0affffbb60 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Mon, 2 Jun 2025 16:53:36 +0800
Subject: [PATCH 2/4] [DAG] Add fneg test.
---
llvm/test/CodeGen/AMDGPU/freeze-binary.ll | 103 +++++-----------------
1 file changed, 22 insertions(+), 81 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
index 4321cedcc8b96..476696e135ea8 100644
--- a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
+++ b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
@@ -1,30 +1,40 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX11
-define float @freeze_fadd(float %input) nounwind {
-; GFX11-LABEL: freeze_fadd:
+
+define float @freeze_fneg(float %input) nounwind {
+; GFX11-LABEL: freeze_fneg:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_add_f32_e32 v0, 2.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
- %x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
+ %x = fneg reassoc nsz arcp contract afn float %input
%y = freeze float %x
- %z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
+ %z = fneg reassoc nsz arcp contract afn float %y
ret float %z
}
-define float @freeze_fadd_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_fadd_nnan:
+define <8 x float> @freeze_fneg_vec(<8 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fneg_vec:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
- %x = fadd nnan contract float %input, 1.000000e+00
+ %x = fneg <8 x float> %input
+ %y = freeze <8 x float> %x
+ %z = fneg <8 x float> %y
+ ret <8 x float> %z
+}
+
+define float @freeze_fadd(float %input) nounwind {
+; GFX11-LABEL: freeze_fadd:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v0, 2.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
%y = freeze float %x
- %z = fadd nnan contract float %y, 1.000000e+00
+ %z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
ret float %z
}
@@ -57,21 +67,6 @@ entry:
ret float %z
}
-define float @freeze_fsub_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_fsub_nnan:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
- %x = fsub nnan contract float %input, 1.000000e+00
- %y = freeze float %x
- %z = fsub nnan contract float %y, 1.000000e+00
- ret float %z
-}
-
define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
; GFX11-LABEL: freeze_fsub_vec:
; GFX11: ; %bb.0: ; %entry
@@ -99,21 +94,6 @@ entry:
ret float %z
}
-define float @freeze_fmul_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_fmul_nnan:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
- %x = fmul nnan contract float %input, 2.000000e+00
- %y = freeze float %x
- %z = fmul nnan contract float %y, 2.000000e+00
- ret float %z
-}
-
define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
; GFX11-LABEL: freeze_fmul_vec:
; GFX11: ; %bb.0: ; %entry
@@ -143,21 +123,6 @@ entry:
ret float %z
}
-define float @freeze_fdiv_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_fdiv_nnan:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mul_f32_e32 v0, 0.5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f32_e32 v0, 0.5, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
- %x = fdiv nnan contract float %input, 2.000000e+00
- %y = freeze float %x
- %z = fdiv nnan contract float %y, 2.000000e+00
- ret float %z
-}
-
define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
; GFX11-LABEL: freeze_fdiv_vec:
; GFX11: ; %bb.0: ; %entry
@@ -195,30 +160,6 @@ entry:
ret float %z
}
-define float @freeze_frem_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_frem_nnan:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_trunc_f32_e32 v1, v1
-; GFX11-NEXT: v_fma_f32 v1, -2.0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v0
-; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_trunc_f32_e32 v2, v2
-; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
- %x = frem nnan contract float %input, 2.000000e+00
- %y = freeze float %x
- %z = frem nnan contract float %y, 2.000000e+00
- ret float %z
-}
-
define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
; GFX11-LABEL: freeze_frem_vec:
; GFX11: ; %bb.0: ; %entry
>From d4d426cdee75104232cdce8cf665d0f33911dabd Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Mon, 2 Jun 2025 17:15:33 +0800
Subject: [PATCH 3/4] [DAG] Update lit test.
---
llvm/test/CodeGen/AMDGPU/freeze-binary.ll | 264 +++++++++++-----------
1 file changed, 126 insertions(+), 138 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
index 476696e135ea8..061595cf7598a 100644
--- a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
+++ b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
@@ -1,12 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX11
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s
define float @freeze_fneg(float %input) nounwind {
-; GFX11-LABEL: freeze_fneg:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fneg:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fneg reassoc nsz arcp contract afn float %input
%y = freeze float %x
%z = fneg reassoc nsz arcp contract afn float %y
@@ -14,11 +13,10 @@ entry:
}
define <8 x float> @freeze_fneg_vec(<8 x float> %input) nounwind {
-; GFX11-LABEL: freeze_fneg_vec:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fneg_vec:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fneg <8 x float> %input
%y = freeze <8 x float> %x
%z = fneg <8 x float> %y
@@ -26,12 +24,11 @@ entry:
}
define float @freeze_fadd(float %input) nounwind {
-; GFX11-LABEL: freeze_fadd:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_add_f32_e32 v0, 2.0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fadd:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_add_f32_e32 v0, 2.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
%y = freeze float %x
%z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
@@ -39,13 +36,12 @@ entry:
}
define <4 x float> @freeze_fadd_vec(<4 x float> %input) nounwind {
-; GFX11-LABEL: freeze_fadd_vec:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
-; GFX11-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fadd_vec:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
+; CHECK-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fadd reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
%y = freeze <4 x float> %x
%z = fadd reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
@@ -53,14 +49,13 @@ entry:
}
define float @freeze_fsub(float %input) nounwind {
-; GFX11-LABEL: freeze_fsub:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fsub:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fsub reassoc nsz arcp contract afn float %input, 1.000000e+00
%y = freeze float %x
%z = fsub reassoc nsz arcp contract afn float %y, 1.000000e+00
@@ -68,13 +63,12 @@ entry:
}
define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
-; GFX11-LABEL: freeze_fsub_vec:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
-; GFX11-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fsub_vec:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
+; CHECK-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fsub reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
%y = freeze <4 x float> %x
%z = fsub reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
@@ -82,12 +76,11 @@ entry:
}
define float @freeze_fmul(float %input) nounwind {
-; GFX11-LABEL: freeze_fmul:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mul_f32_e32 v0, 4.0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fmul:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, 4.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fmul reassoc nsz arcp contract afn float %input, 2.000000e+00
%y = freeze float %x
%z = fmul reassoc nsz arcp contract afn float %y, 2.000000e+00
@@ -95,15 +88,14 @@ entry:
}
define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
-; GFX11-LABEL: freeze_fmul_vec:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
-; GFX11-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
-; GFX11-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
-; GFX11-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fmul_vec:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
+; CHECK-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
+; CHECK-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
+; CHECK-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fmul reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
%y = freeze <8 x float> %x
%z = fmul reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
@@ -111,12 +103,11 @@ entry:
}
define float @freeze_fdiv(float %input) nounwind {
-; GFX11-LABEL: freeze_fdiv:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fdiv:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fdiv reassoc nsz arcp contract afn float %input, 2.000000e+00
%y = freeze float %x
%z = fdiv reassoc nsz arcp contract afn float %y, 2.000000e+00
@@ -124,15 +115,14 @@ entry:
}
define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
-; GFX11-LABEL: freeze_fdiv_vec:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
-; GFX11-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
-; GFX11-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
-; GFX11-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_fdiv_vec:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
+; CHECK-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
+; CHECK-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
+; CHECK-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = fdiv reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
%y = freeze <8 x float> %x
%z = fdiv reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
@@ -140,20 +130,19 @@ entry:
}
define float @freeze_frem(float %input) nounwind {
-; GFX11-LABEL: freeze_frem:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_trunc_f32_e32 v1, v1
-; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
-; GFX11-NEXT: v_trunc_f32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_frem:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-NEXT: v_trunc_f32_e32 v1, v1
+; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0
+; CHECK-NEXT: v_trunc_f32_e32 v1, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = frem reassoc nsz arcp contract afn float %input, 2.000000e+00
%y = freeze float %x
%z = frem reassoc nsz arcp contract afn float %y, 2.000000e+00
@@ -161,61 +150,60 @@ entry:
}
define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
-; GFX11-LABEL: freeze_frem_vec:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
-; GFX11-NEXT: v_trunc_f32_e32 v11, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_trunc_f32_e32 v8, v8
-; GFX11-NEXT: v_trunc_f32_e32 v9, v9
-; GFX11-NEXT: v_mul_f32_e32 v10, 0.5, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
-; GFX11-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_trunc_f32_e32 v10, v10
-; GFX11-NEXT: v_trunc_f32_e32 v9, v7
-; GFX11-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
-; GFX11-NEXT: v_mul_f32_e32 v8, 0.5, v1
-; GFX11-NEXT: v_trunc_f32_e32 v9, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
-; GFX11-NEXT: v_trunc_f32_e32 v8, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v8
-; GFX11-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
-; GFX11-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
-; GFX11-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_trunc_f32_e32 v8, v10
-; GFX11-NEXT: v_trunc_f32_e32 v10, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
-; GFX11-NEXT: v_trunc_f32_e32 v8, v11
-; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
-; GFX11-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_fmac_f32_e32 v7, -4.0, v8
-; GFX11-NEXT: v_trunc_f32_e32 v9, v12
-; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
-; GFX11-NEXT: v_trunc_f32_e32 v9, v11
-; GFX11-NEXT: v_trunc_f32_e32 v11, v3
-; GFX11-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_f32_e32 v3, v3, v11
-; GFX11-NEXT: v_trunc_f32_e32 v8, v10
-; GFX11-NEXT: v_trunc_f32_e32 v10, v12
-; GFX11-NEXT: v_trunc_f32_e32 v12, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_fmac_f32_e32 v2, -2.0, v8
-; GFX11-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_sub_f32_e32 v4, v4, v12
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-entry:
+; CHECK-LABEL: freeze_frem_vec:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
+; CHECK-NEXT: v_trunc_f32_e32 v11, v0
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; CHECK-NEXT: v_trunc_f32_e32 v8, v8
+; CHECK-NEXT: v_trunc_f32_e32 v9, v9
+; CHECK-NEXT: v_mul_f32_e32 v10, 0.5, v6
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; CHECK-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
+; CHECK-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; CHECK-NEXT: v_trunc_f32_e32 v10, v10
+; CHECK-NEXT: v_trunc_f32_e32 v9, v7
+; CHECK-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
+; CHECK-NEXT: v_mul_f32_e32 v8, 0.5, v1
+; CHECK-NEXT: v_trunc_f32_e32 v9, v11
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; CHECK-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
+; CHECK-NEXT: v_trunc_f32_e32 v8, v8
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_fmac_f32_e32 v1, -2.0, v8
+; CHECK-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
+; CHECK-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
+; CHECK-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; CHECK-NEXT: v_trunc_f32_e32 v8, v10
+; CHECK-NEXT: v_trunc_f32_e32 v10, v12
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
+; CHECK-NEXT: v_trunc_f32_e32 v8, v11
+; CHECK-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
+; CHECK-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; CHECK-NEXT: v_fmac_f32_e32 v7, -4.0, v8
+; CHECK-NEXT: v_trunc_f32_e32 v9, v12
+; CHECK-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; CHECK-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
+; CHECK-NEXT: v_trunc_f32_e32 v9, v11
+; CHECK-NEXT: v_trunc_f32_e32 v11, v3
+; CHECK-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; CHECK-NEXT: v_sub_f32_e32 v3, v3, v11
+; CHECK-NEXT: v_trunc_f32_e32 v8, v10
+; CHECK-NEXT: v_trunc_f32_e32 v10, v12
+; CHECK-NEXT: v_trunc_f32_e32 v12, v4
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; CHECK-NEXT: v_fmac_f32_e32 v2, -2.0, v8
+; CHECK-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; CHECK-NEXT: v_sub_f32_e32 v4, v4, v12
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%x = frem reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
%y = freeze <8 x float> %x
%z = frem reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
>From 563148ef7b94d043c876400d352f186db91aebce Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Mon, 2 Jun 2025 17:59:19 +0800
Subject: [PATCH 4/4] [DAG] Update lit test.
---
llvm/test/CodeGen/AMDGPU/freeze-binary.ll | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
index 061595cf7598a..b799d6e6b6e9d 100644
--- a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
+++ b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
@@ -12,17 +12,6 @@ define float @freeze_fneg(float %input) nounwind {
ret float %z
}
-define <8 x float> @freeze_fneg_vec(<8 x float> %input) nounwind {
-; CHECK-LABEL: freeze_fneg_vec:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_setpc_b64 s[30:31]
- %x = fneg <8 x float> %input
- %y = freeze <8 x float> %x
- %z = fneg <8 x float> %y
- ret <8 x float> %z
-}
-
define float @freeze_fadd(float %input) nounwind {
; CHECK-LABEL: freeze_fadd:
; CHECK: ; %bb.0:
More information about the llvm-commits
mailing list