[llvm] [RISCV] Fold LI 1 / SLLI into BSETI during i64 materialization (PR #142348)
Piotr Fusik via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 2 02:34:43 PDT 2025
https://github.com/pfusik updated https://github.com/llvm/llvm-project/pull/142348
>From b72509866496e0413b6f3e1210920168ee3820c3 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 2 Jun 2025 10:41:38 +0200
Subject: [PATCH 1/2] [RISCV][test] Add i64 materialization tests for BSETI
---
llvm/test/CodeGen/RISCV/imm.ll | 126 +++++++++++++++++++
llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll | 29 +++++
2 files changed, 155 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index f324a9bc120ef..fc3af22f082d7 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -4637,3 +4637,129 @@ define i64 @imm64_0xFF7FFFFF7FFFFFFE() {
; RV64-REMAT-NEXT: ret
ret i64 -36028799166447617 ; 0xFF7FFFFF7FFFFFFE
}
+
+define i64 @imm64_0xFFFFFFFF0() {
+; RV32I-LABEL: imm64_0xFFFFFFFF0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a0, -16
+; RV32I-NEXT: li a1, 15
+; RV32I-NEXT: ret
+;
+; RV32IXQCILI-LABEL: imm64_0xFFFFFFFF0:
+; RV32IXQCILI: # %bb.0:
+; RV32IXQCILI-NEXT: li a0, -16
+; RV32IXQCILI-NEXT: li a1, 15
+; RV32IXQCILI-NEXT: ret
+;
+; RV64I-LABEL: imm64_0xFFFFFFFF0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: slli a0, a0, 36
+; RV64I-NEXT: addi a0, a0, -16
+; RV64I-NEXT: ret
+;
+; RV64IZBA-LABEL: imm64_0xFFFFFFFF0:
+; RV64IZBA: # %bb.0:
+; RV64IZBA-NEXT: li a0, 1
+; RV64IZBA-NEXT: slli a0, a0, 36
+; RV64IZBA-NEXT: addi a0, a0, -16
+; RV64IZBA-NEXT: ret
+;
+; RV64IZBB-LABEL: imm64_0xFFFFFFFF0:
+; RV64IZBB: # %bb.0:
+; RV64IZBB-NEXT: li a0, 1
+; RV64IZBB-NEXT: slli a0, a0, 36
+; RV64IZBB-NEXT: addi a0, a0, -16
+; RV64IZBB-NEXT: ret
+;
+; RV64IZBS-LABEL: imm64_0xFFFFFFFF0:
+; RV64IZBS: # %bb.0:
+; RV64IZBS-NEXT: li a0, 1
+; RV64IZBS-NEXT: slli a0, a0, 36
+; RV64IZBS-NEXT: addi a0, a0, -16
+; RV64IZBS-NEXT: ret
+;
+; RV64IXTHEADBB-LABEL: imm64_0xFFFFFFFF0:
+; RV64IXTHEADBB: # %bb.0:
+; RV64IXTHEADBB-NEXT: li a0, 1
+; RV64IXTHEADBB-NEXT: slli a0, a0, 36
+; RV64IXTHEADBB-NEXT: addi a0, a0, -16
+; RV64IXTHEADBB-NEXT: ret
+;
+; RV32-REMAT-LABEL: imm64_0xFFFFFFFF0:
+; RV32-REMAT: # %bb.0:
+; RV32-REMAT-NEXT: li a0, -16
+; RV32-REMAT-NEXT: li a1, 15
+; RV32-REMAT-NEXT: ret
+;
+; RV64-REMAT-LABEL: imm64_0xFFFFFFFF0:
+; RV64-REMAT: # %bb.0:
+; RV64-REMAT-NEXT: li a0, 1
+; RV64-REMAT-NEXT: slli a0, a0, 36
+; RV64-REMAT-NEXT: addi a0, a0, -16
+; RV64-REMAT-NEXT: ret
+ ret i64 68719476720 ; 0xFFFFFFFF0
+}
+
+define i64 @imm64_0x1FFFFFF08() {
+; RV32I-LABEL: imm64_0x1FFFFFF08:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a0, -248
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: ret
+;
+; RV32IXQCILI-LABEL: imm64_0x1FFFFFF08:
+; RV32IXQCILI: # %bb.0:
+; RV32IXQCILI-NEXT: li a0, -248
+; RV32IXQCILI-NEXT: li a1, 1
+; RV32IXQCILI-NEXT: ret
+;
+; RV64I-LABEL: imm64_0x1FFFFFF08:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: slli a0, a0, 33
+; RV64I-NEXT: addi a0, a0, -248
+; RV64I-NEXT: ret
+;
+; RV64IZBA-LABEL: imm64_0x1FFFFFF08:
+; RV64IZBA: # %bb.0:
+; RV64IZBA-NEXT: li a0, 1
+; RV64IZBA-NEXT: slli a0, a0, 33
+; RV64IZBA-NEXT: addi a0, a0, -248
+; RV64IZBA-NEXT: ret
+;
+; RV64IZBB-LABEL: imm64_0x1FFFFFF08:
+; RV64IZBB: # %bb.0:
+; RV64IZBB-NEXT: li a0, 1
+; RV64IZBB-NEXT: slli a0, a0, 33
+; RV64IZBB-NEXT: addi a0, a0, -248
+; RV64IZBB-NEXT: ret
+;
+; RV64IZBS-LABEL: imm64_0x1FFFFFF08:
+; RV64IZBS: # %bb.0:
+; RV64IZBS-NEXT: li a0, 1
+; RV64IZBS-NEXT: slli a0, a0, 33
+; RV64IZBS-NEXT: addi a0, a0, -248
+; RV64IZBS-NEXT: ret
+;
+; RV64IXTHEADBB-LABEL: imm64_0x1FFFFFF08:
+; RV64IXTHEADBB: # %bb.0:
+; RV64IXTHEADBB-NEXT: li a0, 1
+; RV64IXTHEADBB-NEXT: slli a0, a0, 33
+; RV64IXTHEADBB-NEXT: addi a0, a0, -248
+; RV64IXTHEADBB-NEXT: ret
+;
+; RV32-REMAT-LABEL: imm64_0x1FFFFFF08:
+; RV32-REMAT: # %bb.0:
+; RV32-REMAT-NEXT: li a0, -248
+; RV32-REMAT-NEXT: li a1, 1
+; RV32-REMAT-NEXT: ret
+;
+; RV64-REMAT-LABEL: imm64_0x1FFFFFF08:
+; RV64-REMAT: # %bb.0:
+; RV64-REMAT-NEXT: li a0, 1
+; RV64-REMAT-NEXT: slli a0, a0, 33
+; RV64-REMAT-NEXT: addi a0, a0, -248
+; RV64-REMAT-NEXT: ret
+ ret i64 8589934344 ; 0x1FFFFFF08
+}
diff --git a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
index 449e983fb6b52..0a7dd57d03969 100644
--- a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
+++ b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
@@ -385,3 +385,32 @@ define i64 @xornofff(i64 %x) {
%xor = xor i64 %x, -1152921504606846721
ret i64 %xor
}
+
+define i64 @and_or_or(i64 %x, i64 %y) {
+; RV32-LABEL: and_or_or:
+; RV32: # %bb.0:
+; RV32-NEXT: ori a1, a1, -2
+; RV32-NEXT: ori a0, a0, 1
+; RV32-NEXT: ori a3, a3, 1
+; RV32-NEXT: ori a2, a2, -2
+; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: and a1, a1, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: and_or_or:
+; RV64: # %bb.0:
+; RV64-NEXT: li a2, -1
+; RV64-NEXT: slli a2, a2, 33
+; RV64-NEXT: addi a2, a2, 1
+; RV64-NEXT: or a0, a0, a2
+; RV64-NEXT: li a2, 1
+; RV64-NEXT: slli a2, a2, 33
+; RV64-NEXT: addi a2, a2, -2
+; RV64-NEXT: or a1, a1, a2
+; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: ret
+ %a = or i64 %x, -8589934591
+ %b = or i64 %y, 8589934590
+ %c = and i64 %a, %b
+ ret i64 %c
+}
>From fee65e5fe22cb3be4b9474e4a829efb81777c324 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 2 Jun 2025 10:41:59 +0200
Subject: [PATCH 2/2] [RISCV] Fold LI 1 / SLLI into BSETI during i64
materialization
My first approach was to avoid emitting LI 1 / SLLI in the first place.
Unfortunately, that favors BSETI C / ADDI -1 over LI -1 / SRLI 64-C
even though the latter has both instructions compressible.
This is because the code assumes in several places that a two-instruction
sequence (here: BSETI / ADDI) cannot be improved.
Another possible approach would be to keep LI 1 / SLLI if it is to be
later replaced with SRLI. This would be harder to grasp than simply
patching LI 1 / SLLI with BSETI.
---
.../Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 7 ++++
llvm/test/CodeGen/RISCV/imm.ll | 6 ++--
llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll | 33 ++++++++++++-------
3 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 8ea2548258fdb..323bcfc11625a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -353,6 +353,13 @@ InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
} while (Hi != 0);
Res = TmpSeq;
}
+
+ // Fold LI 1 + SLLI into BSETI.
+ if (Res[0].getOpcode() == RISCV::ADDI && Res[0].getImm() == 1 &&
+ Res[1].getOpcode() == RISCV::SLLI) {
+ Res.erase(Res.begin()); // Remove ADDI.
+ Res.front() = Inst(RISCV::BSETI, Res.front().getImm()); // Patch SLLI.
+ }
}
// Perform optimization with BCLRI in the Zbs extension.
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index fc3af22f082d7..418407d9b7cd6 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -4674,8 +4674,7 @@ define i64 @imm64_0xFFFFFFFF0() {
;
; RV64IZBS-LABEL: imm64_0xFFFFFFFF0:
; RV64IZBS: # %bb.0:
-; RV64IZBS-NEXT: li a0, 1
-; RV64IZBS-NEXT: slli a0, a0, 36
+; RV64IZBS-NEXT: bseti a0, zero, 36
; RV64IZBS-NEXT: addi a0, a0, -16
; RV64IZBS-NEXT: ret
;
@@ -4737,8 +4736,7 @@ define i64 @imm64_0x1FFFFFF08() {
;
; RV64IZBS-LABEL: imm64_0x1FFFFFF08:
; RV64IZBS: # %bb.0:
-; RV64IZBS-NEXT: li a0, 1
-; RV64IZBS-NEXT: slli a0, a0, 33
+; RV64IZBS-NEXT: bseti a0, zero, 33
; RV64IZBS-NEXT: addi a0, a0, -248
; RV64IZBS-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
index 0a7dd57d03969..eb81e0f13d14a 100644
--- a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
+++ b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
@@ -397,18 +397,27 @@ define i64 @and_or_or(i64 %x, i64 %y) {
; RV32-NEXT: and a1, a1, a3
; RV32-NEXT: ret
;
-; RV64-LABEL: and_or_or:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, -1
-; RV64-NEXT: slli a2, a2, 33
-; RV64-NEXT: addi a2, a2, 1
-; RV64-NEXT: or a0, a0, a2
-; RV64-NEXT: li a2, 1
-; RV64-NEXT: slli a2, a2, 33
-; RV64-NEXT: addi a2, a2, -2
-; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: and a0, a0, a1
-; RV64-NEXT: ret
+; NOZBS64-LABEL: and_or_or:
+; NOZBS64: # %bb.0:
+; NOZBS64-NEXT: li a2, -1
+; NOZBS64-NEXT: slli a2, a2, 33
+; NOZBS64-NEXT: addi a2, a2, 1
+; NOZBS64-NEXT: or a0, a0, a2
+; NOZBS64-NEXT: li a2, 1
+; NOZBS64-NEXT: slli a2, a2, 33
+; NOZBS64-NEXT: addi a2, a2, -2
+; NOZBS64-NEXT: or a1, a1, a2
+; NOZBS64-NEXT: and a0, a0, a1
+; NOZBS64-NEXT: ret
+;
+; ZBS64-LABEL: and_or_or:
+; ZBS64: # %bb.0:
+; ZBS64-NEXT: bseti a2, zero, 33
+; ZBS64-NEXT: addi a2, a2, -2
+; ZBS64-NEXT: orn a0, a0, a2
+; ZBS64-NEXT: or a1, a1, a2
+; ZBS64-NEXT: and a0, a0, a1
+; ZBS64-NEXT: ret
%a = or i64 %x, -8589934591
%b = or i64 %y, 8589934590
%c = and i64 %a, %b
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