[llvm] promoteMUBUFLoadStoreScalarOffset (PR #142328)

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github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index b4667968b..1260fc254 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -428,16 +428,16 @@ static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) {
       case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_exact:
       case AMDGPU::BUFFER_LOAD_DWORD_IDXEN:
       case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_exact:
-      case AMDGPU::BUFFER_LOAD_DWORD_OFFEN://
-      case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact://
+      case AMDGPU::BUFFER_LOAD_DWORD_OFFEN:       //
+      case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact: //
       case AMDGPU::BUFFER_LOAD_DWORD_OFFSET:
       case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_exact:
       case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:
       case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN_exact:
       case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN:
       case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN_exact:
-      case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN://
-      case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_exact://
+      case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN:       //
+      case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_exact: //
       case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET:
       case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET_exact:
         return BUFFER_LOAD;
@@ -2093,25 +2093,33 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
   if (!Base.isReg())
     return;
 
-  MachineInstr *Def = MRI->getUniqueVRegDef(Base.getReg());//REG_SEQUENCE %LO:vgpr_32, %subreg.sub0, %HI:vgpr_32, %subreg.sub1
+  MachineInstr *Def = MRI->getUniqueVRegDef(
+      Base.getReg()); // REG_SEQUENCE %LO:vgpr_32, %subreg.sub0, %HI:vgpr_32,
+                      // %subreg.sub1
   if (!Def || Def->getOpcode() != AMDGPU::REG_SEQUENCE
       || Def->getNumOperands() != 5)
     return;
 
-  MachineOperand BaseLo = Def->getOperand(1);//%LO:vgpr_32
-  MachineOperand BaseHi = Def->getOperand(3);//%HI:vgpr_32
+  MachineOperand BaseLo = Def->getOperand(1); //%LO:vgpr_32
+  MachineOperand BaseHi = Def->getOperand(3); //%HI:vgpr_32
   if (!BaseLo.isReg() || !BaseHi.isReg())
     return;
 
-  MachineInstr *BaseLoDef = MRI->getUniqueVRegDef(BaseLo.getReg());//%LO:vgpr_32, %c:sreg_64_xexec = V_ADD_CO_U32_e64 %BASE_LO:vgpr_32, %103:sgpr_32,
-  MachineInstr *BaseHiDef = MRI->getUniqueVRegDef(BaseHi.getReg());//%HI:vgpr_32, = V_ADDC_U32_e64 %BASE_HI:vgpr_32, 0, killed %c:sreg_64_xexec
+  MachineInstr *BaseLoDef = MRI->getUniqueVRegDef(
+      BaseLo.getReg()); //%LO:vgpr_32, %c:sreg_64_xexec = V_ADD_CO_U32_e64
+                        //%BASE_LO:vgpr_32, %103:sgpr_32,
+  MachineInstr *BaseHiDef = MRI->getUniqueVRegDef(
+      BaseHi.getReg()); //%HI:vgpr_32, = V_ADDC_U32_e64 %BASE_HI:vgpr_32, 0,
+                        //killed %c:sreg_64_xexec
 
   if (!BaseLoDef || BaseLoDef->getOpcode() != AMDGPU::V_ADD_CO_U32_e64 ||
       !BaseHiDef || BaseHiDef->getOpcode() != AMDGPU::V_ADDC_U32_e64)
     return;
 
-  const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0);//%BASE_LO:vgpr_32
-  const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1);//%103:sgpr_32
+  const auto *Src0 =
+      TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); //%BASE_LO:vgpr_32
+  const auto *Src1 =
+      TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); //%103:sgpr_32
 
   auto Offset0P = extractConstOffset(*Src0);
   if (Offset0P)
@@ -2121,12 +2129,13 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
       return;
     BaseLo = *Src0;
   }
-//BaseLo = %103:sgpr_32
+  // BaseLo = %103:sgpr_32
   if (!BaseLo.isReg())
     return;
 
-  Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0);// %BASE_HI:vgpr_32
-  Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1);// 0
+  Src0 = TII->getNamedOperand(*BaseHiDef,
+                              AMDGPU::OpName::src0); // %BASE_HI:vgpr_32
+  Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); // 0
 
   if (Src0->isImm())
     std::swap(Src0, Src1);
@@ -2134,14 +2143,14 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
   if (!Src1->isImm() || Src0->isImm())
     return;
 
-  uint64_t Offset1 = Src1->getImm(); //0
-  BaseHi = *Src0;//%BASE_HI:vgpr_32
+  uint64_t Offset1 = Src1->getImm(); // 0
+  BaseHi = *Src0;                    //%BASE_HI:vgpr_32
 
   if (!BaseHi.isReg())
     return;
 
-  Addr.Base.LoReg = BaseLo.getReg();//%103:sgpr_32
-  Addr.Base.HiReg = BaseHi.getReg();//%BASE_HI:vgpr_32
+  Addr.Base.LoReg = BaseLo.getReg(); //%103:sgpr_32
+  Addr.Base.HiReg = BaseHi.getReg(); //%BASE_HI:vgpr_32
   Addr.Base.LoSubReg = BaseLo.getSubReg();
   Addr.Base.HiSubReg = BaseHi.getSubReg();
   Addr.Offset = (*Offset0P & 0x00000000ffffffff) | (Offset1 << 32);
@@ -2300,34 +2309,43 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
 }
 
 bool SILoadStoreOptimizer::promoteMUBUFLoadStoreScalarOffset(
-    MachineInstr &MI) const{
-  if(!SIInstrInfo::isMUBUF(MI))
-      return false;
+    MachineInstr &MI) const {
+  if (!SIInstrInfo::isMUBUF(MI))
+    return false;
   LLVM_DEBUG(dbgs() << "tryToPromoteMUBUFLoadStoreScalarOffset:"; MI.dump());
   auto vaddr = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
-  if(!vaddr)  return false;
+  if (!vaddr)
+    return false;
   LLVM_DEBUG(dbgs() << "\n vaddr:"; vaddr->dump());
   MachineInstr *Def = MRI->getUniqueVRegDef(vaddr->getReg());
-  if(!Def)  return false;
+  if (!Def)
+    return false;
   LLVM_DEBUG(dbgs() << "\n def:"; Def->dump());
   auto opsrc0 = TII->getNamedOperand(*Def, AMDGPU::OpName::src0);
-  if(!opsrc0) return false;
+  if (!opsrc0)
+    return false;
   auto opsrc1 = TII->getNamedOperand(*Def, AMDGPU::OpName::src1);
-  if(!opsrc1) return false;
+  if (!opsrc1)
+    return false;
   LLVM_DEBUG(dbgs() << "\n opsrc0:"; opsrc0->dump());
   LLVM_DEBUG(dbgs() << "\n opsrc1:"; opsrc1->dump());
-  auto isopsrc0scalarreg = TII->getRegisterInfo().isSGPRClass(MRI->getRegClass(opsrc0->getReg()));
-  auto isopsrc1scalarreg = TII->getRegisterInfo().isSGPRClass(MRI->getRegClass(opsrc1->getReg()));
-  LLVM_DEBUG(dbgs() << "\n isopsrc0scalarreg:" << isopsrc0scalarreg << " isopsrc1scalarreg:" << isopsrc1scalarreg;);
-  if(!(isopsrc0scalarreg ^ isopsrc1scalarreg))  return false;
+  auto isopsrc0scalarreg =
+      TII->getRegisterInfo().isSGPRClass(MRI->getRegClass(opsrc0->getReg()));
+  auto isopsrc1scalarreg =
+      TII->getRegisterInfo().isSGPRClass(MRI->getRegClass(opsrc1->getReg()));
+  LLVM_DEBUG(dbgs() << "\n isopsrc0scalarreg:" << isopsrc0scalarreg
+                    << " isopsrc1scalarreg:" << isopsrc1scalarreg;);
+  if (!(isopsrc0scalarreg ^ isopsrc1scalarreg))
+    return false;
   auto scalarOp = isopsrc0scalarreg ? opsrc0 : opsrc1;
-  
-    // if (!BaseLoDef || BaseLoDef->getOpcode() != AMDGPU::V_ADD_CO_U32_e64 ||
-    //   !BaseHiDef || BaseHiDef->getOpcode() != AMDGPU::V_ADDC_U32_e64)
-    // return;
 
-  // const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0);//%BASE_LO:vgpr_32
-  // const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1);//%103:sgpr_32
+  // if (!BaseLoDef || BaseLoDef->getOpcode() != AMDGPU::V_ADD_CO_U32_e64 ||
+  //   !BaseHiDef || BaseHiDef->getOpcode() != AMDGPU::V_ADDC_U32_e64)
+  // return;
+
+  // const auto *Src0 = TII->getNamedOperand(*BaseLoDef,
+  // AMDGPU::OpName::src0);//%BASE_LO:vgpr_32 const auto *Src1 =
+  // TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1);//%103:sgpr_32
 
   return false;
 }

``````````

</details>


https://github.com/llvm/llvm-project/pull/142328