[llvm] [PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (PR #142220)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Fri May 30 14:55:33 PDT 2025
https://github.com/lei137 created https://github.com/llvm/llvm-project/pull/142220
Remove explicit register arithmetic from spilling ACC and STXVP code.
>From 9dd17376c7fbaf4205ca701a1979bdddf6b1bdb3 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 30 May 2025 11:15:07 -0500
Subject: [PATCH 1/5] clean up code gen for register mapping used in stxvp
spilling
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 109 ++++++++++++++------
1 file changed, 77 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 51902ad218d1c..d82dd5285f8d8 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1238,41 +1238,50 @@ static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
#endif
}
+#if 0
static void spillRegPairs(MachineBasicBlock &MBB,
MachineBasicBlock::iterator II, DebugLoc DL,
const TargetInstrInfo &TII, Register SrcReg,
- unsigned FrameIndex, bool IsLittleEndian,
- bool IsKilled, bool TwoPairs) {
- unsigned Offset = 0;
+ unsigned FrameIndex, bool IsLittleEndian) {
+ MachineInstr &MI = *II;
+ bool IsKilled = MI.getOperand(0).isKill();
+ unsigned Offset = IsLittleEndian ? 48 : 0;
+
// The register arithmetic in this function does not support virtual
// registers.
+ /*
assert(!SrcReg.isVirtual() &&
"Spilling register pairs does not support virtual registers.");
+ */
- if (TwoPairs)
- Offset = IsLittleEndian ? 48 : 0;
- else
- Offset = IsLittleEndian ? 16 : 0;
- Register Reg = (SrcReg > PPC::VSRp15) ? PPC::V0 + (SrcReg - PPC::VSRp16) * 2
- : PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(Reg, getKillRegState(IsKilled)),
- FrameIndex, Offset);
+ Register RegP0 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0);
+ Register RegP1 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(Reg + 1, getKillRegState(IsKilled)),
- FrameIndex, Offset);
- if (TwoPairs) {
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(Reg + 2, getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(Reg + 3, getKillRegState(IsKilled)),
- FrameIndex, Offset);
- }
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
}
+#endif
/// Remove any STXVP[X] instructions and split them out into a pair of
/// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
@@ -1290,8 +1299,19 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
Register SrcReg = MI.getOperand(0).getReg();
bool IsLittleEndian = Subtarget.isLittleEndian();
bool IsKilled = MI.getOperand(0).isKill();
- spillRegPairs(MBB, II, DL, TII, SrcReg, FrameIndex, IsLittleEndian, IsKilled,
- /* TwoPairs */ false);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? 16 : 0);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? 0 : 16);
+
// Discard the original instruction.
MBB.erase(II);
}
@@ -1321,8 +1341,8 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- Register SrcReg = MI.getOperand(0).getReg();
bool IsKilled = MI.getOperand(0).isKill();
+ Register SrcReg = MI.getOperand(0).getReg();
bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
Register Reg =
@@ -1337,10 +1357,35 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
// adjust the offset of the store that is within the 64-byte stack slot.
if (IsPrimed)
BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
- if (DisableAutoPairedVecSt)
- spillRegPairs(MBB, II, DL, TII, Reg, FrameIndex, IsLittleEndian, IsKilled,
- /* TwoPairs */ true);
- else {
+ if (DisableAutoPairedVecSt) {
+ unsigned Offset = IsLittleEndian ? 48 : 0;
+ Register RegP0 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0);
+ Register RegP1 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1);
+
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ Offset += IsLittleEndian ? -16 : 16;
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ } else {
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
.addReg(Reg, getKillRegState(IsKilled)),
FrameIndex, IsLittleEndian ? 32 : 0);
>From 1734a2353a78abfd4de075b22d5af4d9f5c60b5c Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 30 May 2025 12:28:17 -0500
Subject: [PATCH 2/5] simpliy handling for spilling acc reg with stx
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 89 ++++-----------------
1 file changed, 16 insertions(+), 73 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index d82dd5285f8d8..69bac86b0ce8f 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1238,51 +1238,6 @@ static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
#endif
}
-#if 0
-static void spillRegPairs(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator II, DebugLoc DL,
- const TargetInstrInfo &TII, Register SrcReg,
- unsigned FrameIndex, bool IsLittleEndian) {
- MachineInstr &MI = *II;
- bool IsKilled = MI.getOperand(0).isKill();
- unsigned Offset = IsLittleEndian ? 48 : 0;
-
- // The register arithmetic in this function does not support virtual
- // registers.
- /*
- assert(!SrcReg.isVirtual() &&
- "Spilling register pairs does not support virtual registers.");
- */
-
- Register RegP0 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0);
- Register RegP1 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1);
-
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
-}
-#endif
-
/// Remove any STXVP[X] instructions and split them out into a pair of
/// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
/// the command line.
@@ -1305,7 +1260,6 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx0),
getKillRegState(IsKilled)),
FrameIndex, IsLittleEndian ? 16 : 0);
-
addFrameReference(
BuildMI(MBB, II, DL, TII.get(PPC::STXV))
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx1),
@@ -1358,33 +1312,22 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
if (IsPrimed)
BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
if (DisableAutoPairedVecSt) {
- unsigned Offset = IsLittleEndian ? 48 : 0;
- Register RegP0 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0);
- Register RegP1 = TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1);
-
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP0, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx0),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
- Offset += IsLittleEndian ? -16 : 16;
- addFrameReference(
- BuildMI(MBB, II, DL, TII.get(PPC::STXV))
- .addReg(TargetRegisterInfo::getSubReg(RegP1, PPC::sub_vsx1),
- getKillRegState(IsKilled)),
- FrameIndex, Offset);
+ auto spillPair = [&](Register Reg, int Offset) {
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx0),
+ getKillRegState(IsKilled)),
+ FrameIndex, Offset);
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXV))
+ .addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx1),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? Offset - 16 : Offset + 16);
+ };
+ spillPair(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0),
+ IsLittleEndian ? 48 : 0);
+ spillPair(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
+ IsLittleEndian ? 16 : 32);
} else {
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
.addReg(Reg, getKillRegState(IsKilled)),
>From 9bbd8418528b4f55f75304b26565ec038accaaab Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 30 May 2025 13:01:19 -0500
Subject: [PATCH 3/5] remove un-intentional code move
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 69bac86b0ce8f..f97afbc10f2e1 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1295,8 +1295,8 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- bool IsKilled = MI.getOperand(0).isKill();
Register SrcReg = MI.getOperand(0).getReg();
+ bool IsKilled = MI.getOperand(0).isKill();
bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
Register Reg =
>From 7c51b50aa7cf8467eb3f1f71c4d069b363acbf1c Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 30 May 2025 16:15:02 -0500
Subject: [PATCH 4/5] clean up acc register allocation code
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index f97afbc10f2e1..e8b0fafc6fa80 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1255,6 +1255,9 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
bool IsLittleEndian = Subtarget.isLittleEndian();
bool IsKilled = MI.getOperand(0).isKill();
+ assert(!SrcReg.isVirtual() &&
+ "Spilling register pairs does not support virtual registers.");
+
addFrameReference(
BuildMI(MBB, II, DL, TII.get(PPC::STXV))
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_vsx0),
@@ -1299,8 +1302,6 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
bool IsKilled = MI.getOperand(0).isKill();
bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
- Register Reg =
- PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
bool IsLittleEndian = Subtarget.isLittleEndian();
emitAccSpillRestoreInfo(MBB, IsPrimed, false);
@@ -1329,12 +1330,16 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
spillPair(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
IsLittleEndian ? 16 : 32);
} else {
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
- .addReg(Reg, getKillRegState(IsKilled)),
- FrameIndex, IsLittleEndian ? 32 : 0);
- addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
- .addReg(Reg + 1, getKillRegState(IsKilled)),
- FrameIndex, IsLittleEndian ? 0 : 32);
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
+ .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? 32 : 0);
+ addFrameReference(
+ BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
+ .addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
+ getKillRegState(IsKilled)),
+ FrameIndex, IsLittleEndian ? 0 : 32);
}
if (IsPrimed && !IsKilled)
BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
>From 3fab473161051e2b6f2728681c65dfc546a2baee Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 30 May 2025 16:53:36 -0500
Subject: [PATCH 5/5] update assert check
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index e8b0fafc6fa80..7c0d2e0dbec27 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1255,8 +1255,8 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
bool IsLittleEndian = Subtarget.isLittleEndian();
bool IsKilled = MI.getOperand(0).isKill();
- assert(!SrcReg.isVirtual() &&
- "Spilling register pairs does not support virtual registers.");
+ assert(PPC::VSRpRCRegClass.contains(SrcReg) &&
+ "Expecting STXVP to be utilizing a VSRp register.");
addFrameReference(
BuildMI(MBB, II, DL, TII.get(PPC::STXV))
More information about the llvm-commits
mailing list