[llvm] [AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and GFX10 (PR #142188)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

> The types are not uniform across gfx9 and gfx10. For example, on gfx1010 and gfx900 src2 is 32 bits and on gfx1030 and gfx90a src2 is 16 bits. And the compiler won't be able to make use of opsel without true16 or some intrinsic change. Why do you want to do this?

So this is for src2 only? This is confusing though as ISA spec says:
```
D0.u32 = 32'U(({ S0.u32, S1.u32 } >> S2.u32[4 : 0]) & 0xffffffffLL)
```
I.e., [4:0] is explicit w/o any mention of the opsel.

https://github.com/llvm/llvm-project/pull/142188