[llvm] [DAGCombiner] Teach SearchForAndLoads to handle an AND with 2 constant operands. (PR #142062)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri May 30 09:29:49 PDT 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/142062
>From 2506cffc5fcacc2be9a94a694eca455811f68520 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 29 May 2025 14:28:54 -0700
Subject: [PATCH 1/3] Pre-commit test
---
llvm/test/CodeGen/RISCV/pr142004.ll | 34 +++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/pr142004.ll
diff --git a/llvm/test/CodeGen/RISCV/pr142004.ll b/llvm/test/CodeGen/RISCV/pr142004.ll
new file mode 100644
index 0000000000000..22e1c993799ee
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr142004.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
+
+ at f = global i64 0, align 8
+ at d = global i64 0, align 8
+ at e = global i32 0, align 8
+
+define i32 @foo(i32 %x) {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a1, %hi(f)
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: lui a3, %hi(d)
+; CHECK-NEXT: lbu a1, %lo(f)(a1)
+; CHECK-NEXT: lhu a3, %lo(d)(a3)
+; CHECK-NEXT: addiw a2, a2, -1
+; CHECK-NEXT: and a4, a0, a2
+; CHECK-NEXT: xor a0, a1, a2
+; CHECK-NEXT: or a0, a0, a3
+; CHECK-NEXT: lui a1, %hi(e)
+; CHECK-NEXT: sw a4, %lo(e)(a1)
+; CHECK-NEXT: ret
+entry:
+ %1 = load i64, ptr @f, align 8
+ %conv1 = and i64 %1, 255
+ %conv2 = xor i64 %conv1, 255
+ %2 = load i64, ptr @d, align 8
+ %or = or i64 %conv2, %2
+ %conv3 = trunc i64 %or to i32
+ %conv4 = and i32 %conv3, 65535
+ %and = and i32 %x, 65535
+ store i32 %and, ptr @e
+ ret i32 %conv4
+}
>From 9c11eede4ca738373c5e4f55ef79545b7c4fe349 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 29 May 2025 16:08:00 -0700
Subject: [PATCH 2/3] [DAGCombiner] Teach SearchForAndLoads to handle an AND
with 2 constant operands.
If opaque constants are involved we can have an AND with 2 constant
operands that hasn't been simplified. If this is the case, we need
to modify at least one of the constants if it is out of range.
Fixes #142004
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 11 +++++++++--
llvm/test/CodeGen/RISCV/pr142004.ll | 15 +++++++--------
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e05f85ea3bd8e..fe5310aff6c73 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6812,7 +6812,8 @@ bool DAGCombiner::SearchForAndLoads(SDNode *N,
// Some constants may need fixing up later if they are too large.
if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
- if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
+ if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR ||
+ N->getOpcode() == ISD::AND) &&
(Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
NodesWithConsts.insert(N);
continue;
@@ -6927,7 +6928,13 @@ bool DAGCombiner::BackwardsPropagateMask(SDNode *N) {
SDValue Op0 = LogicN->getOperand(0);
SDValue Op1 = LogicN->getOperand(1);
- if (isa<ConstantSDNode>(Op0))
+ // We only need to fix AND if both inputs are constants. And we only need
+ // to fix one of the constants.
+ if (LogicN->getOpcode() == ISD::AND &&
+ (!isa<ConstantSDNode>(Op0) || !isa<ConstantSDNode>(Op1)))
+ continue;
+
+ if (isa<ConstantSDNode>(Op0) && LogicN->getOpcode() != ISD::AND)
Op0 =
DAG.getNode(ISD::AND, SDLoc(Op0), Op0.getValueType(), Op0, MaskOp);
diff --git a/llvm/test/CodeGen/RISCV/pr142004.ll b/llvm/test/CodeGen/RISCV/pr142004.ll
index 22e1c993799ee..709644e49e704 100644
--- a/llvm/test/CodeGen/RISCV/pr142004.ll
+++ b/llvm/test/CodeGen/RISCV/pr142004.ll
@@ -9,16 +9,15 @@ define i32 @foo(i32 %x) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a1, %hi(f)
-; CHECK-NEXT: lui a2, 16
-; CHECK-NEXT: lui a3, %hi(d)
+; CHECK-NEXT: lui a2, %hi(d)
; CHECK-NEXT: lbu a1, %lo(f)(a1)
-; CHECK-NEXT: lhu a3, %lo(d)(a3)
-; CHECK-NEXT: addiw a2, a2, -1
-; CHECK-NEXT: and a4, a0, a2
-; CHECK-NEXT: xor a0, a1, a2
-; CHECK-NEXT: or a0, a0, a3
+; CHECK-NEXT: lhu a2, %lo(d)(a2)
+; CHECK-NEXT: slli a0, a0, 48
+; CHECK-NEXT: srli a3, a0, 48
+; CHECK-NEXT: xori a0, a1, 255
+; CHECK-NEXT: or a0, a0, a2
; CHECK-NEXT: lui a1, %hi(e)
-; CHECK-NEXT: sw a4, %lo(e)(a1)
+; CHECK-NEXT: sw a3, %lo(e)(a1)
; CHECK-NEXT: ret
entry:
%1 = load i64, ptr @f, align 8
>From f1d92ee7ec324bc0d36ef2e3fdad49e45ac885f6 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 30 May 2025 09:00:47 -0700
Subject: [PATCH 3/3] fixup! Use assert
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index fe5310aff6c73..15f44e49ab5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6812,9 +6812,9 @@ bool DAGCombiner::SearchForAndLoads(SDNode *N,
// Some constants may need fixing up later if they are too large.
if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
- if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR ||
- N->getOpcode() == ISD::AND) &&
- (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
+ assert(ISD::isBitwiseLogicOp(N->getOpcode()) &&
+ "Expected bitwise logic operation");
+ if ((Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
NodesWithConsts.insert(N);
continue;
}
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