[llvm] [AMDGPU] Extend SRA i64 simplification for shift amts in range [33:62] (PR #138913)

[via llvm-commits]

================
@@ -4153,22 +4153,23 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
   SDLoc SL(N);
   unsigned RHSVal = RHS->getZExtValue();
 
-  // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
-  if (RHSVal == 32) {
+  // For C >= 32
+  // (sra i64:x, C) -> build_pair (sra hi_32(x), C - 32), (sra hi_32(x), 31)
----------------
LU-JOHN wrote:

> Can also add nuw to the shift https://alive2.llvm.org/ce/z/ocnLgT and nuw nsw on the sub: https://alive2.llvm.org/ce/z/tRDbS2
> 
> And if the shift is exact, can preserve shift on the new right shift: https://alive2.llvm.org/ce/z/rie9oU

This PR is only handling shifts by a constant.  The sub is only in the alive2 verification to validate multiple shift values.

This PR does not use a shift and or to construct the 64-bit value as in the old alive2 verification.  Instead it uses insertelement and bitcast, https://alive2.llvm.org/ce/z/4bs2mv.


https://github.com/llvm/llvm-project/pull/138913