[llvm] [AArch64] Enable fixed-length vector support for partial-reductions (PR #142032)

[Nicholas Guy via llvm-commits]

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@@ -2225,6 +2233,26 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
   bool PreferNEON = VT.is64BitVector() || VT.is128BitVector();
   bool PreferSVE = !PreferNEON && Subtarget->isSVEAvailable();
 
+  if (EnablePartialReduceNodes) {
+    unsigned NumElts = VT.getVectorNumElements();
+    if (VT.getVectorElementType() == MVT::i64) {
+      setPartialReduceMLAAction(VT, MVT::getVectorVT(MVT::i8, NumElts * 8),
+                                Custom);
+      setPartialReduceMLAAction(VT, MVT::getVectorVT(MVT::i16, NumElts * 4),
+                                Custom);
+      setPartialReduceMLAAction(VT, MVT::getVectorVT(MVT::i32, NumElts * 2),
+                                Custom);
+    } else if (VT.getVectorElementType() == MVT::i32) {
+      setPartialReduceMLAAction(VT, MVT::getVectorVT(MVT::i8, NumElts * 4),
+                                Custom);
+      setPartialReduceMLAAction(VT, MVT::getVectorVT(MVT::i16, NumElts * 2),
+                                Custom);
+    } else if (VT.getVectorElementType() == MVT::i16) {
+      setPartialReduceMLAAction(VT, MVT::getVectorVT(MVT::i8, NumElts * 2),
+                                Custom);
+    }
+  }
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NickGuy-Arm wrote:

How does this approach differ from the explicit assignments above? Do we need both, or can we get rid of one of them?

https://github.com/llvm/llvm-project/pull/142032