[llvm] [SPIRV]Added support for extension SPV_INTEL_arbitrary_precision_fixed_point (PR #136085)
Aadesh Premkumar via llvm-commits
llvm-commits at lists.llvm.org
Thu May 29 22:00:54 PDT 2025
https://github.com/aadeshps-mcw updated https://github.com/llvm/llvm-project/pull/136085
>From 9c074478a19a26ab3de00d9c3c7ff57c86beb2d4 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Tue, 13 May 2025 11:59:12 +0530
Subject: [PATCH 1/3] --Updated the test file
---
llvm/docs/SPIRVUsage.rst | 2 +
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 76 +++++-
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 14 +
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 5 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 26 ++
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 21 ++
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 2 +
...arbitrary-precision-fixed-point-numbers.ll | 255 ++++++++++++++++++
8 files changed, 399 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 1858bda6160d4..e43770dc72332 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -217,6 +217,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
- Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix.
* - ``SPV_INTEL_int4``
- Adds support for 4-bit integer type, and allow this type to be used in cooperative matrices.
+ * - ``SPV_INTEL_arbitrary_precision_fixed_point``
+ - Add instructions for fixed point arithmetic. The extension works without SPV_INTEL_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index f73a39c6ee9da..a15caa1f01550 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -697,7 +697,8 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
if (Call->isSpirvOp())
- return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
+ return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call,
+ Register(0));
Register ScopeRegister =
buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -2325,6 +2326,77 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
}
+static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call,
+ unsigned Opcode, MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ MachineRegisterInfo *MRI = MIRBuilder.getMRI();
+ SmallVector<uint32_t, 1> ImmArgs;
+ Register InputReg = Call->Arguments[0];
+ const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
+ bool IsSRet = RetTy->isVoidTy();
+
+ if (IsSRet) {
+ const LLT ValTy = MRI->getType(InputReg);
+ Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy);
+ SPIRVType *InstructionType =
+ GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
+ InputReg = Call->Arguments[1];
+ auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg));
+ Register PtrInputReg;
+ if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) {
+ LLT InputLLT = MRI->getType(InputReg);
+ PtrInputReg = MRI->createGenericVirtualRegister(InputLLT);
+ SPIRVType *PtrType =
+ GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
+ MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOLoad,
+ InputLLT.getSizeInBytes(), Align(4));
+ MIRBuilder.buildLoad(PtrInputReg, InputReg, *MMO1);
+ MRI->setRegClass(PtrInputReg, &SPIRV::iIDRegClass);
+ GR->assignSPIRVTypeToVReg(PtrType, PtrInputReg, MIRBuilder.getMF());
+ }
+
+ for (unsigned index = 2; index < 7; index++) {
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
+ }
+
+ // Emit the instruction
+ auto MIB = MIRBuilder.buildInstr(Opcode)
+ .addDef(ActualRetValReg)
+ .addUse(GR->getSPIRVTypeID(InstructionType));
+ if (PtrInputReg)
+ MIB.addUse(PtrInputReg);
+ else
+ MIB.addUse(InputReg);
+
+ for (uint32_t Imm : ImmArgs)
+ MIB.addImm(Imm);
+ unsigned Size = ValTy.getSizeInBytes();
+ // Store result to the pointer passed in Arg[0]
+ MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOStore, Size, Align(4));
+ MRI->setRegClass(ActualRetValReg, &SPIRV::pIDRegClass);
+ MIRBuilder.buildStore(ActualRetValReg, Call->Arguments[0], *MMO);
+ return true;
+ } else {
+ for (unsigned index = 1; index < 6; index++)
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
+
+ return buildOpFromWrapper(MIRBuilder, Opcode, Call,
+ GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
+ }
+}
+
+static bool generateAPFixedPointInst(const SPIRV::IncomingCall *Call,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
+ unsigned Opcode =
+ SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
+
+ return buildAPFixedPointInst(Call, Opcode, MIRBuilder, GR);
+}
+
static bool
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
@@ -2929,6 +3001,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
case SPIRV::BindlessINTEL:
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
+ case SPIRV::ArbitraryPrecisionFixedPoint:
+ return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
case SPIRV::TernaryBitwiseINTEL:
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
case SPIRV::Block2DLoadStore:
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index 6842e5ff067cf..f389a07e1a372 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -69,6 +69,7 @@ def ExtendedBitOps : BuiltinGroup;
def BindlessINTEL : BuiltinGroup;
def TernaryBitwiseINTEL : BuiltinGroup;
def Block2DLoadStore : BuiltinGroup;
+def ArbitraryPrecisionFixedPoint : BuiltinGroup;
//===----------------------------------------------------------------------===//
// Class defining a demangled builtin record. The information in the record
@@ -1144,6 +1145,19 @@ defm : DemangledNativeBuiltin<"clock_read_hilo_device", OpenCL_std, KernelClock,
defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
+//SPV_INTEL_arbitrary_precision_fixed_point
+defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
+
//===----------------------------------------------------------------------===//
// Class defining an atomic instruction on floating-point numbers.
//
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index fbaca4e0e4d81..27ff34d9588bd 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -100,7 +100,10 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
{"SPV_INTEL_2d_block_io",
SPIRV::Extension::Extension::SPV_INTEL_2d_block_io},
- {"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4}};
+ {"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
+ {"SPV_INTEL_arbitrary_precision_fixed_point",
+ SPIRV::Extension::Extension::
+ SPV_INTEL_arbitrary_precision_fixed_point}};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 338f6809a3e46..827bc0a88bbb6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -953,3 +953,29 @@ def OpSubgroup2DBlockPrefetchINTEL: Op<6234, (outs), (ins ID:$element_size, ID:$
def OpSubgroup2DBlockStoreINTEL: Op<6235, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
ID:$block_count, ID:$src_ptr, ID:$dst_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord),
"OpSubgroup2DBlockStoreINTEL $element_size $block_width $block_height $block_count $src_ptr $dst_base_ptr $memory_width $memory_height $memory_pitch $coord">;
+
+
+
+//SPV_INTEL_arbitrary_precision_fixed_point
+def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
\ No newline at end of file
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 2fdd54fdfc390..92b04376e0cb6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1516,6 +1516,27 @@ void addInstrRequirements(const MachineInstr &MI,
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
break;
+ case SPIRV::OpFixedCosINTEL:
+ case SPIRV::OpFixedSinINTEL:
+ case SPIRV::OpFixedCosPiINTEL:
+ case SPIRV::OpFixedSinPiINTEL:
+ case SPIRV::OpFixedExpINTEL:
+ case SPIRV::OpFixedLogINTEL:
+ case SPIRV::OpFixedRecipINTEL:
+ case SPIRV::OpFixedSqrtINTEL:
+ case SPIRV::OpFixedSinCosINTEL:
+ case SPIRV::OpFixedSinCosPiINTEL:
+ case SPIRV::OpFixedRsqrtINTEL:
+ if (!ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
+ report_fatal_error("This instruction requires the "
+ "following SPIR-V extension: "
+ "SPV_INTEL_arbitrary_precision_fixed_point",
+ false);
+ Reqs.addExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
+ Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
+ break;
case SPIRV::OpGroupIMulKHR:
case SPIRV::OpGroupFMulKHR:
case SPIRV::OpGroupBitwiseAndKHR:
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index ca8a9a9997a8b..16ac95fd10017 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -318,6 +318,7 @@ defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
defm SPV_INTEL_subgroup_matrix_multiply_accumulate : ExtensionOperand<121>;
defm SPV_INTEL_2d_block_io : ExtensionOperand<122>;
defm SPV_INTEL_int4 : ExtensionOperand<123>;
+defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<124>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -525,6 +526,7 @@ defm Subgroup2DBlockTransformINTEL : CapabilityOperand<6229, 0, 0, [SPV_INTEL_2d
defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
+defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
new file mode 100644
index 0000000000000..0e003d217ace7
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
@@ -0,0 +1,255 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - -filetype=obj | spirv-val %}
+
+
+; CHECK-DAG: OpCapability Kernel
+; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersINTEL
+; CHECK-DAG: OpCapability ArbitraryPrecisionFixedPointINTEL
+; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_fixed_point"
+; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+
+; CHECK-DAG: %[[Ty_8:[0-9]+]] = OpTypeInt 8 0
+; CHECK-DAG: %[[Ty_13:[0-9]+]] = OpTypeInt 13 0
+; CHECK-DAG: %[[Ty_5:[0-9]+]] = OpTypeInt 5 0
+; CHECK-DAG: %[[Ty_3:[0-9]+]] = OpTypeInt 3 0
+; CHECK-DAG: %[[Ty_11:[0-9]+]] = OpTypeInt 11 0
+; CHECK-DAG: %[[Ty_10:[0-9]+]] = OpTypeInt 10 0
+; CHECK-DAG: %[[Ty_17:[0-9]+]] = OpTypeInt 17 0
+; CHECK-DAG: %[[Ty_35:[0-9]+]] = OpTypeInt 35 0
+; CHECK-DAG: %[[Ty_28:[0-9]+]] = OpTypeInt 28 0
+; CHECK-DAG: %[[Ty_31:[0-9]+]] = OpTypeInt 31 0
+; CHECK-DAG: %[[Ty_40:[0-9]+]] = OpTypeInt 40 0
+; CHECK-DAG: %[[Ty_60:[0-9]+]] = OpTypeInt 60 0
+; CHECK-DAG: %[[Ty_16:[0-9]+]] = OpTypeInt 16 0
+; CHECK-DAG: %[[Ty_64:[0-9]+]] = OpTypeInt 64 0
+; CHECK-DAG: %[[Ty_44:[0-9]+]] = OpTypeInt 44 0
+; CHECK-DAG: %[[Ty_34:[0-9]+]] = OpTypeInt 34 0
+; CHECK-DAG: %[[Ty_51:[0-9]+]] = OpTypeInt 51 0
+
+; CHECK: %[[Sqrt_InId:[0-9]+]] = OpLoad %[[Ty_13]]
+; CHECK-NEXT: %[[#]] = OpFixedSqrtINTEL %[[Ty_5]] %[[Sqrt_InId]] 0 2 2 0 0
+
+; CHECK: %[[Recip_InId:[0-9]+]] = OpLoad %[[Ty_3]]
+; CHECK-NEXT: %[[#]] = OpFixedRecipINTEL %[[Ty_8]] %[[Recip_InId]] 1 4 4 0 0
+
+; CHECK: %[[Rsqrt_InId:[0-9]+]] = OpLoad %[[Ty_11]]
+; CHECK-NEXT: %[[#]] = OpFixedRsqrtINTEL %[[Ty_10]] %[[Rsqrt_InId]] 0 8 6 0 0
+
+; CHECK: %[[Sin_InId:[0-9]+]] = OpLoad %[[Ty_17]]
+; CHECK-NEXT: %[[#]] = OpFixedSinINTEL %[[Ty_11]] %[[Sin_InId]] 1 7 5 0 0
+
+; CHECK: %[[Cos_InId:[0-9]+]] = OpLoad %[[Ty_35]]
+; CHECK-NEXT: %[[#]] = OpFixedCosINTEL %[[Ty_28]] %[[Cos_InId]] 0 9 3 0 0
+
+; CHECK: %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_31]]
+; CHECK-NEXT: %[[#]] = OpFixedSinCosINTEL %[[Ty_40]] %[[SinCos_InId]] 1 10 12 0 0
+
+; CHECK: %[[SinPi_InId:[0-9]+]] = OpLoad %[[Ty_60]]
+; CHECK-NEXT: %[[#]] = OpFixedSinPiINTEL %[[Ty_5]] %[[SinPi_InId]] 0 2 2 0 0
+
+; CHECK: %[[CosPi_InId:[0-9]+]] = OpLoad %[[Ty_28]]
+; CHECK-NEXT: %[[#]] = OpFixedCosPiINTEL %[[Ty_16]] %[[CosPi_InId]] 0 8 5 0 0
+
+; CHECK: %[[SinCosPi_InId:[0-9]+]] = OpLoad %[[Ty_13]]
+; CHECK-NEXT: %[[#]] = OpFixedSinCosPiINTEL %[[Ty_10]] %[[SinCosPi_InId]] 0 2 2 0 0
+
+; CHECK: %[[Log_InId:[0-9]+]] = OpLoad %[[Ty_64]]
+; CHECK-NEXT: %[[#]] = OpFixedLogINTEL %[[Ty_44]] %[[Log_InId]] 1 24 22 0 0
+
+; CHECK: %[[Exp_InId:[0-9]+]] = OpLoad %[[Ty_44]]
+; CHECK-NEXT: %[[#]] = OpFixedExpINTEL %[[Ty_34]] %[[Exp_InId]] 0 20 20 0 0
+
+; CHECK: %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_34]]
+; CHECK-NEXT: %[[SinCos_ResultId:[0-9]+]] = OpFixedSinCosINTEL %[[Ty_51]] %[[SinCos_InId]] 1 3 2 0 0
+; CHECK-NEXT: OpStore %[[#]] %[[SinCos_ResultId]]
+
+; CHECK: %[[ResId:[0-9]+]] = OpLoad %[[Ty_51]]
+; CHECK-NEXT: OpStore %[[PtrId:[0-9]+]] %[[ResId]]
+; CHECK-NEXT: %[[ExpInId2:[0-9]+]] = OpLoad %[[Ty_51]] %[[PtrId]]
+; CHECK-NEXT: %[[#]] = OpFixedExpINTEL %[[Ty_51]] %[[ExpInId2]] 0 20 20 0 0
+
+%"class._ZTSZ4mainE3$_0.anon" = type { i8 }
+
+define dso_local spir_kernel void @_ZTSZ4mainE15kernel_function() !kernel_arg_addr_space !{} !kernel_arg_access_qual !{} !kernel_arg_type !{} !kernel_arg_base_type !{} !kernel_arg_type_qual !{} {
+entry:
+ %0 = alloca %"class._ZTSZ4mainE3$_0.anon", align 1
+ %1 = addrspacecast ptr %0 to ptr addrspace(4)
+ call spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %1)
+ ret void
+}
+
+define internal spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %this) align 2 {
+entry:
+ %this.addr = alloca ptr addrspace(4), align 8
+ store ptr addrspace(4) %this, ptr %this.addr, align 8
+ call spir_func void @_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z5recipILi3ELi8ELb1ELi4ELi4EEvv()
+ call spir_func void @_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv()
+ call spir_func void @_Z3sinILi17ELi11ELb1ELi7ELi5EEvv()
+ call spir_func void @_Z3cosILi35ELi28ELb0ELi9ELi3EEvv()
+ call spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv()
+ call spir_func void @_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv()
+ call spir_func void @_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv()
+ call spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv()
+ call spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_()
+ call spir_func void @_Z3expILi51ELi51ELb0ELi20ELi20EEvv()
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv() {
+entry:
+ %in_ptr = alloca i13, align 2
+ %out_ptr = alloca i5, align 1
+ %in_val = load i13, ptr %in_ptr, align 2
+ %res = call spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext %in_val, i1 zeroext false, i32 2, i32 2, i32 0, i32 0)
+ store i5 %res, ptr %out_ptr, align 1
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z5recipILi3ELi8ELb1ELi4ELi4EEvv() {
+entry:
+ %in_ptr = alloca i3, align 1
+ %out_ptr = alloca i8, align 1
+ %in_val = load i3, ptr %in_ptr, align 1
+ %res = call spir_func signext i8 @_Z23__spirv_FixedRecipINTELILi3ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i3 signext %in_val, i1 zeroext true, i32 4, i32 4, i32 0, i32 0)
+ store i8 %res, ptr %out_ptr, align 1
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv() {
+entry:
+ %in_ptr = alloca i11, align 2
+ %out_ptr = alloca i10, align 2
+ %in_val = load i11, ptr %in_ptr, align 2
+ %res = call spir_func signext i10 @_Z23__spirv_FixedRsqrtINTELILi11ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i11 signext %in_val, i1 zeroext false, i32 8, i32 6, i32 0, i32 0)
+ store i10 %res, ptr %out_ptr, align 2
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3sinILi17ELi11ELb1ELi7ELi5EEvv() {
+entry:
+ %in_ptr = alloca i17, align 4
+ %out_ptr = alloca i11, align 2
+ %in_val = load i17, ptr %in_ptr, align 4
+ %res = call spir_func signext i11 @_Z21__spirv_FixedSinINTELILi17ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i17 signext %in_val, i1 zeroext true, i32 7, i32 5, i32 0, i32 0)
+ store i11 %res, ptr %out_ptr, align 2
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3cosILi35ELi28ELb0ELi9ELi3EEvv() {
+entry:
+ %in_ptr = alloca i35, align 8
+ %out_ptr = alloca i28, align 4
+ %in_val = load i35, ptr %in_ptr, align 8
+ %res = call spir_func signext i28 @_Z21__spirv_FixedCosINTELILi35ELi28EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i35 signext %in_val, i1 zeroext false, i32 9, i32 3, i32 0, i32 0)
+ store i28 %res, ptr %out_ptr, align 4
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv() {
+entry:
+ %in_ptr = alloca i31, align 4
+ %out_ptr = alloca i40, align 8
+ %in_val = load i31, ptr %in_ptr, align 4
+ %res = call spir_func i40 @_Z24__spirv_FixedSinCosINTELILi31ELi20EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i31 signext %in_val, i1 zeroext true, i32 10, i32 12, i32 0, i32 0)
+ store i40 %res, ptr %out_ptr, align 8
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv() {
+entry:
+ %in_ptr = alloca i60, align 8
+ %out_ptr = alloca i5, align 1
+ %in_val = load i60, ptr %in_ptr, align 8
+ %res = call spir_func signext i5 @_Z23__spirv_FixedSinPiINTELILi60ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i60 signext %in_val, i1 zeroext false, i32 2, i32 2, i32 0, i32 0)
+ store i5 %res, ptr %out_ptr, align 1
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv() {
+entry:
+ %in_ptr = alloca i28, align 4
+ %out_ptr = alloca i16, align 2
+ %in_val = load i28, ptr %in_ptr, align 4
+ %res = call spir_func signext i16 @_Z23__spirv_FixedCosPiINTELILi28ELi16EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i28 signext %in_val, i1 zeroext false, i32 8, i32 5, i32 0, i32 0)
+ store i16 %res, ptr %out_ptr, align 2
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv() {
+entry:
+ %in_ptr = alloca i13, align 2
+ %out_ptr = alloca i10, align 2
+ %in_val = load i13, ptr %in_ptr, align 2
+ %res = call spir_func signext i10 @_Z26__spirv_FixedSinCosPiINTELILi13ELi5EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i13 signext %in_val, i1 zeroext false, i32 2, i32 2, i32 0, i32 0)
+ store i10 %res, ptr %out_ptr, align 2
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv() {
+entry:
+ %in_ptr = alloca i64, align 8
+ %out_ptr = alloca i44, align 8
+ %in_val = load i64, ptr %in_ptr, align 8
+ %res = call spir_func i44 @_Z21__spirv_FixedLogINTELILi64ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i64 %in_val, i1 zeroext true, i32 24, i32 22, i32 0, i32 0)
+ store i44 %res, ptr %out_ptr, align 8
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv() {
+entry:
+ %in_ptr = alloca i44, align 8
+ %out_ptr = alloca i34, align 8
+ %in_val = load i44, ptr %in_ptr, align 8
+ %res = call spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i44 %in_val, i1 zeroext false, i32 20, i32 20, i32 0, i32 0)
+ store i34 %res, ptr %out_ptr, align 8
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_() {
+entry:
+ %tmp = alloca i34, align 8
+ %out_ptr = alloca i51, align 8
+ %in_ptr = addrspacecast ptr %tmp to ptr addrspace(4)
+ %out_s = addrspacecast ptr %out_ptr to ptr addrspace(4)
+ %in_val = load i34, ptr addrspace(4) %in_ptr, align 8
+ call spir_func void @_Z24__spirv_FixedSinCosINTELILi34ELi51EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8 %out_s, i34 %in_val, i1 zeroext true, i32 3, i32 2, i32 0, i32 0)
+ ret void
+}
+
+define linkonce_odr dso_local spir_func void @_Z3expILi51ELi51ELb0ELi20ELi20EEvv() {
+entry:
+ %a = alloca i51, align 8
+ %a.ascast = addrspacecast ptr %a to ptr addrspace(4)
+ %ap_fixed_Exp = alloca i51, align 8
+ %ap_fixed_Exp.ascast = addrspacecast ptr %ap_fixed_Exp to ptr addrspace(4)
+ %tmp = alloca i51, align 8
+ %tmp.ascast = addrspacecast ptr %tmp to ptr addrspace(4)
+ %indirect-arg-temp = alloca i51, align 8
+ %0 = load i51, ptr addrspace(4) %a.ascast, align 8
+ store i51 %0, ptr %indirect-arg-temp, align 8
+ call spir_func void @_Z21__spirv_FixedExpINTELILi51ELi51EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(
+ ptr addrspace(4) sret(i51) align 8 %tmp.ascast,
+ ptr byval(i64) align 8 %indirect-arg-temp,
+ i1 zeroext false, i32 20, i32 20, i32 0, i32 0)
+ %1 = load i51, ptr addrspace(4) %tmp.ascast, align 8
+ store i51 %1, ptr addrspace(4) %ap_fixed_Exp.ascast, align 8
+ ret void
+}
+
+declare dso_local spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i13 @_Z22__spirv_FixedSqrtINTELILi5ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i5 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i8 @_Z23__spirv_FixedRecipINTELILi3ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i3 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i10 @_Z23__spirv_FixedRsqrtINTELILi11ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i11 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i11 @_Z21__spirv_FixedSinINTELILi17ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i17 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i28 @_Z21__spirv_FixedCosINTELILi35ELi28EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i35, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func i40 @_Z24__spirv_FixedSinCosINTELILi31ELi20EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i31 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i5 @_Z23__spirv_FixedSinPiINTELILi60ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i60, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i16 @_Z23__spirv_FixedCosPiINTELILi28ELi16EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i28 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func signext i10 @_Z26__spirv_FixedSinCosPiINTELILi13ELi5EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func i44 @_Z21__spirv_FixedLogINTELILi64ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i64, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i44, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func void @_Z24__spirv_FixedSinCosINTELILi34ELi51EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8, i34, i1 zeroext, i32, i32, i32, i32)
+declare dso_local spir_func void @_Z21__spirv_FixedExpINTELILi51ELi51EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8, ptr byval(i51) align 8, i1 zeroext, i32, i32, i32, i32)
>From 06f356084afe330f61fdb68c3a4993a1d3454625 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Fri, 30 May 2025 10:29:06 +0530
Subject: [PATCH 2/3] --Updated files after the conflict resolution
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 4 ++--
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index a15caa1f01550..f6a175e90927e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -3001,12 +3001,12 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
case SPIRV::BindlessINTEL:
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
- case SPIRV::ArbitraryPrecisionFixedPoint:
- return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
case SPIRV::TernaryBitwiseINTEL:
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
case SPIRV::Block2DLoadStore:
return generate2DBlockIOINTELInst(Call.get(), MIRBuilder, GR);
+ case SPIRV::ArbitraryPrecisionFixedPoint:
+ return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
}
return false;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 827bc0a88bbb6..553e2105b9f3e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -954,8 +954,6 @@ def OpSubgroup2DBlockStoreINTEL: Op<6235, (outs), (ins ID:$element_size, ID:$blo
ID:$block_count, ID:$src_ptr, ID:$dst_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord),
"OpSubgroup2DBlockStoreINTEL $element_size $block_width $block_height $block_count $src_ptr $dst_base_ptr $memory_width $memory_height $memory_pitch $coord">;
-
-
//SPV_INTEL_arbitrary_precision_fixed_point
def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
"$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
>From 5bf4c87ff2d9c3545f5109441a37506cad0b7730 Mon Sep 17 00:00:00 2001
From: Aadesh Premkumar <aadesh.premkumar at multicorewareinc.com>
Date: Fri, 30 May 2025 10:30:45 +0530
Subject: [PATCH 3/3] Update SPIRVInstrInfo.td
---
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 553e2105b9f3e..fedc8ab76c01d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -976,4 +976,4 @@ def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$i
def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
"$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
- "$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
\ No newline at end of file
+ "$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
More information about the llvm-commits
mailing list