[llvm] [SPIRV] Support for the extension SPV_INTEL_fpga_argument_interfaces (PR #140231)
Aadesh Premkumar via llvm-commits
llvm-commits at lists.llvm.org
Thu May 29 21:52:02 PDT 2025
https://github.com/aadeshps-mcw updated https://github.com/llvm/llvm-project/pull/140231
>From 36f68cc33890aa7b82dc1d71d02afbdff1e05eb0 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Fri, 16 May 2025 15:33:11 +0530
Subject: [PATCH] --Added support for the extension
SPV_INTEL_fpga_argument_interfaces --Added test files for the extension
SPV_INTEL_fpga_argument_interfaces
---
llvm/docs/SPIRVUsage.rst | 2 +
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 22 ++++++++--
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 4 +-
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 11 +++++
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 10 +++++
.../sycl-kernel-arg-annotation.ll | 42 +++++++++++++++++++
6 files changed, 86 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 1858bda6160d4..cc086bfbcedc8 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -217,6 +217,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
- Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix.
* - ``SPV_INTEL_int4``
- Adds support for 4-bit integer type, and allow this type to be used in cooperative matrices.
+ * - ``SPV_INTEL_fpga_argument_interfaces``
+ - Adds kernel argument decorations that influence the interfaces built for for Field Programmable Gate Array (FPGA) kernel arguments.
To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index 5991a9af6364d..df70b28c4d965 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -283,6 +283,18 @@ getExecutionModel(const SPIRVSubtarget &STI, const Function &F) {
report_fatal_error("This HLSL entry point is not supported by this backend.");
}
+static bool shouldSkipOperands(SPIRV::Decoration::Decoration Dec) {
+ switch (Dec) {
+ case SPIRV::Decoration::StableKernelArgumentINTEL:
+ case SPIRV::Decoration::RegisterMapKernelArgumentINTEL:
+ case SPIRV::Decoration::ConduitKernelArgumentINTEL:
+ case SPIRV::Decoration::Restrict:
+ return true;
+ default:
+ return false;
+ }
+}
+
bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
ArrayRef<ArrayRef<Register>> VRegs,
@@ -375,10 +387,12 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
auto Dec =
static_cast<SPIRV::Decoration::Decoration>(Const->getZExtValue());
std::vector<uint32_t> DecVec;
- for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
- ConstantInt *Const = getConstInt(MD2, j);
- assert(Const && "MDOperand should be ConstantInt");
- DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
+ if (!shouldSkipOperands(Dec)) {
+ for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
+ ConstantInt *Const = getConstInt(MD2, j);
+ assert(Const && "MDOperand should be ConstantInt");
+ DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
+ }
}
buildOpDecorate(VRegs[i][0], MIRBuilder, Dec, DecVec);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index fbaca4e0e4d81..9ac4a0dc6a7b4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -100,7 +100,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
{"SPV_INTEL_2d_block_io",
SPIRV::Extension::Extension::SPV_INTEL_2d_block_io},
- {"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4}};
+ {"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
+ {"SPV_INTEL_fpga_argument_interfaces",
+ SPIRV::Extension::Extension::SPV_INTEL_fpga_argument_interfaces}};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 2fdd54fdfc390..1552825e62b06 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -920,6 +920,17 @@ static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex,
} else if (Dec == SPIRV::Decoration::FPMaxErrorDecorationINTEL) {
Reqs.addRequirements(SPIRV::Capability::FPMaxErrorINTEL);
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fp_max_error);
+ } else if (Dec == SPIRV::Decoration::ConduitKernelArgumentINTEL ||
+ Dec == SPIRV::Decoration::RegisterMapKernelArgumentINTEL ||
+ Dec == SPIRV::Decoration::MMHostInterfaceAddressWidthINTEL ||
+ Dec == SPIRV::Decoration::MMHostInterfaceDataWidthINTEL ||
+ Dec == SPIRV::Decoration::MMHostInterfaceLatencyINTEL ||
+ Dec == SPIRV::Decoration::MMHostInterfaceReadWriteModeINTEL ||
+ Dec == SPIRV::Decoration::MMHostInterfaceMaxBurstINTEL ||
+ Dec == SPIRV::Decoration::MMHostInterfaceWaitRequestINTEL ||
+ Dec == SPIRV::Decoration::StableKernelArgumentINTEL) {
+ Reqs.addRequirements(SPIRV::Capability::FPGAArgumentInterfacesINTEL);
+ Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fpga_argument_interfaces);
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index ca8a9a9997a8b..1bda28d1f06e6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -525,6 +525,7 @@ defm Subgroup2DBlockTransformINTEL : CapabilityOperand<6229, 0, 0, [SPV_INTEL_2d
defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
+defm FPGAArgumentInterfacesINTEL : CapabilityOperand<6174, 0, 0, [SPV_INTEL_fpga_argument_interfaces], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
@@ -1276,6 +1277,15 @@ defm FunctionFloatingPointModeINTEL : DecorationOperand<6080, 0, 0, [], [Functio
defm AliasScopeINTEL : DecorationOperand<5914, 0, 0, [], [MemoryAccessAliasingINTEL]>;
defm NoAliasINTEL : DecorationOperand<5915, 0, 0, [], [MemoryAccessAliasingINTEL]>;
defm FPMaxErrorDecorationINTEL : DecorationOperand<6170, 0, 0, [], [FPMaxErrorINTEL]>;
+defm ConduitKernelArgumentINTEL : DecorationOperand<6175, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm RegisterMapKernelArgumentINTEL: DecorationOperand<6176, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceAddressWidthINTEL: DecorationOperand<6177, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceDataWidthINTEL: DecorationOperand<6178, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceLatencyINTEL: DecorationOperand<6179, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceReadWriteModeINTEL: DecorationOperand<6180, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceMaxBurstINTEL: DecorationOperand<6181, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceWaitRequestINTEL: DecorationOperand<6182, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm StableKernelArgumentINTEL: DecorationOperand<6183, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
//===----------------------------------------------------------------------===//
// Multiclass used to define BuiltIn enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll
new file mode 100644
index 0000000000000..c052d4c63dcf4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll
@@ -0,0 +1,42 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_argument_interfaces %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; CHECK: OpCapability FPGAArgumentInterfacesINTEL
+; CHECK: OpExtension "SPV_INTEL_fpga_argument_interfaces"
+; CHECK: OpName %[[ID:[0-9]+]] "_arg_p"
+; CHECK: OpDecorate %[[ID]] Alignment 4
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceAddressWidthINTEL 32
+; CHECK: OpDecorate %[[ID]] ConduitKernelArgumentINTEL
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceDataWidthINTEL 64
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceLatencyINTEL 1
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceMaxBurstINTEL 3
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceReadWriteModeINTEL 2
+; CHECK: OpDecorate %[[ID]] RegisterMapKernelArgumentINTEL
+; CHECK: OpDecorate %[[ID]] StableKernelArgumentINTEL
+; CHECK: OpDecorate %[[ID]] Restrict
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceWaitRequestINTEL 5
+
+$_ZTS4MyIP = comdat any
+
+; Function Attrs: convergent mustprogress norecurse
+define weak_odr dso_local spir_kernel void @_ZTS4MyIP(ptr addrspace(4) noundef %_arg_p) #0 comdat !spirv.ParameterDecorations !1588
+; CHECK-LLVM-DAG: !spirv.ParameterDecorations ![[PARMDECOR:[0-9]+]]
+{
+entry:
+ ret void
+}
+
+!1587 = !{i32 -1}
+!1588 = !{!1589}
+!1589 = !{!1590, !1591, !1593, !1594, !1595, !1596, !1597, !1598, !1599, !1600, !1601}
+!1590 = !{i32 44, i32 4}
+!1591 = !{i32 6177, i32 32}
+!1593 = !{i32 6175, i32 1}
+!1594 = !{i32 6178, i32 64}
+!1595 = !{i32 6179, i32 1}
+!1596 = !{i32 6181, i32 3}
+!1597 = !{i32 6180, i32 2}
+!1598 = !{i32 6176, i32 1}
+!1599 = !{i32 6183, i32 1}
+!1600 = !{i32 19, i32 1}
+!1601 = !{i32 6182, i32 5}
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