[llvm] [AMDGPU] Extend SRA i64 simplification for shift amts in range [33:62] (PR #138913)

[via llvm-commits]

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@@ -4153,22 +4153,23 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
   SDLoc SL(N);
   unsigned RHSVal = RHS->getZExtValue();
 
-  // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
-  if (RHSVal == 32) {
+  // For C >= 32
+  // (sra i64:x, C) -> build_pair (sra hi_32(x), C - 32), (sra hi_32(x), 31)
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LU-JOHN wrote:

Alive2 verification with 8/16-bit sizes: https://alive2.llvm.org/ce/z/YWP8qy.

https://github.com/llvm/llvm-project/pull/138913