[llvm] [RISCV] Fix coalescing vsetvlis when AVL and vl registers are the same (PR #141941)

[Min-Yih Hsu via llvm-commits]

================
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-linux-gnu"
+
+define void @pr141907(ptr %0) #0 {
----------------
mshockwave wrote:

nounwind?

https://github.com/llvm/llvm-project/pull/141941