[llvm] [ARM] Remove unused enable-arm-3-addr-conv (PR #141850)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu May 29 09:31:19 PDT 2025
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/141850
>From bd6201419d7be328e00a4213700604a2c05fce97 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Wed, 28 May 2025 21:30:01 +0100
Subject: [PATCH] [ARM] Remove unused enable-arm-3-addr-conv
This code is not enabled by default and has no tests, having been added back in
10043e215bcfd. It can be safely removed to help keep things simpler.
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 173 -----------------------
llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 3 -
2 files changed, 176 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 69bc84a6733c0..4b029fb4be204 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -76,10 +76,6 @@ using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "ARMGenInstrInfo.inc"
-static cl::opt<bool>
-EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
- cl::desc("Enable ARM 2-addr to 3-addr conv"));
-
/// ARM_MLxEntry - Record information about MLA / MLS instructions.
struct ARM_MLxEntry {
uint16_t MLxOpc; // MLA / MLS opcode
@@ -175,175 +171,6 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
return MHR;
}
-MachineInstr *
-ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
- LiveIntervals *LIS) const {
- // FIXME: Thumb2 support.
-
- if (!EnableARM3Addr)
- return nullptr;
-
- MachineFunction &MF = *MI.getParent()->getParent();
- uint64_t TSFlags = MI.getDesc().TSFlags;
- bool isPre = false;
- switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
- default: return nullptr;
- case ARMII::IndexModePre:
- isPre = true;
- break;
- case ARMII::IndexModePost:
- break;
- }
-
- // Try splitting an indexed load/store to an un-indexed one plus an add/sub
- // operation.
- unsigned MemOpc = getUnindexedOpcode(MI.getOpcode());
- if (MemOpc == 0)
- return nullptr;
-
- MachineInstr *UpdateMI = nullptr;
- MachineInstr *MemMI = nullptr;
- unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
- const MCInstrDesc &MCID = MI.getDesc();
- unsigned NumOps = MCID.getNumOperands();
- bool isLoad = !MI.mayStore();
- const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
- const MachineOperand &Base = MI.getOperand(2);
- const MachineOperand &Offset = MI.getOperand(NumOps - 3);
- Register WBReg = WB.getReg();
- Register BaseReg = Base.getReg();
- Register OffReg = Offset.getReg();
- unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
- ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
- switch (AddrMode) {
- default: llvm_unreachable("Unknown indexed op!");
- case ARMII::AddrMode2: {
- bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
- unsigned Amt = ARM_AM::getAM2Offset(OffImm);
- if (OffReg == 0) {
- if (ARM_AM::getSOImmVal(Amt) == -1)
- // Can't encode it in a so_imm operand. This transformation will
- // add more than 1 instruction. Abandon!
- return nullptr;
- UpdateMI = BuildMI(MF, MI.getDebugLoc(),
- get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
- .addReg(BaseReg)
- .addImm(Amt)
- .add(predOps(Pred))
- .add(condCodeOp());
- } else if (Amt != 0) {
- ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
- unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
- UpdateMI = BuildMI(MF, MI.getDebugLoc(),
- get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
- .addReg(BaseReg)
- .addReg(OffReg)
- .addReg(0)
- .addImm(SOOpc)
- .add(predOps(Pred))
- .add(condCodeOp());
- } else
- UpdateMI = BuildMI(MF, MI.getDebugLoc(),
- get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
- .addReg(BaseReg)
- .addReg(OffReg)
- .add(predOps(Pred))
- .add(condCodeOp());
- break;
- }
- case ARMII::AddrMode3 : {
- bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
- unsigned Amt = ARM_AM::getAM3Offset(OffImm);
- if (OffReg == 0)
- // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
- UpdateMI = BuildMI(MF, MI.getDebugLoc(),
- get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
- .addReg(BaseReg)
- .addImm(Amt)
- .add(predOps(Pred))
- .add(condCodeOp());
- else
- UpdateMI = BuildMI(MF, MI.getDebugLoc(),
- get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
- .addReg(BaseReg)
- .addReg(OffReg)
- .add(predOps(Pred))
- .add(condCodeOp());
- break;
- }
- }
-
- std::vector<MachineInstr*> NewMIs;
- if (isPre) {
- if (isLoad)
- MemMI =
- BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
- .addReg(WBReg)
- .addImm(0)
- .addImm(Pred);
- else
- MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
- .addReg(MI.getOperand(1).getReg())
- .addReg(WBReg)
- .addReg(0)
- .addImm(0)
- .addImm(Pred);
- NewMIs.push_back(MemMI);
- NewMIs.push_back(UpdateMI);
- } else {
- if (isLoad)
- MemMI =
- BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
- .addReg(BaseReg)
- .addImm(0)
- .addImm(Pred);
- else
- MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
- .addReg(MI.getOperand(1).getReg())
- .addReg(BaseReg)
- .addReg(0)
- .addImm(0)
- .addImm(Pred);
- if (WB.isDead())
- UpdateMI->getOperand(0).setIsDead();
- NewMIs.push_back(UpdateMI);
- NewMIs.push_back(MemMI);
- }
-
- // Transfer LiveVariables states, kill / dead info.
- if (LV) {
- for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.getReg().isVirtual()) {
- Register Reg = MO.getReg();
-
- LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
- if (MO.isDef()) {
- MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
- if (MO.isDead())
- LV->addVirtualRegisterDead(Reg, *NewMI);
- }
- if (MO.isUse() && MO.isKill()) {
- for (unsigned j = 0; j < 2; ++j) {
- // Look at the two new MI's in reverse order.
- MachineInstr *NewMI = NewMIs[j];
- if (!NewMI->readsRegister(Reg, /*TRI=*/nullptr))
- continue;
- LV->addVirtualRegisterKilled(Reg, *NewMI);
- if (VI.removeKill(MI))
- VI.Kills.push_back(NewMI);
- break;
- }
- }
- }
- }
- }
-
- MachineBasicBlock &MBB = *MI.getParent();
- MBB.insert(MI, NewMIs[1]);
- MBB.insert(MI, NewMIs[0]);
- return NewMIs[0];
-}
-
// Branch analysis.
// Cond vector output format:
// 0 elements indicates an unconditional branch
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 987f5a0e3d824..71de3c6ad597a 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -125,9 +125,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
- MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
- LiveIntervals *LIS) const override;
-
virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
const ARMSubtarget &getSubtarget() const { return Subtarget; }
More information about the llvm-commits
mailing list