[llvm] 4c88873 - [SPARC][IAS] Add definitions for OSA 2011 instructions
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 29 08:17:02 PDT 2025
Author: Koakuma
Date: 2025-05-29T22:16:58+07:00
New Revision: 4c88873be83e2d212e412459c02d05006c5f0069
URL: https://github.com/llvm/llvm-project/commit/4c88873be83e2d212e412459c02d05006c5f0069
DIFF: https://github.com/llvm/llvm-project/commit/4c88873be83e2d212e412459c02d05006c5f0069.diff
LOG: [SPARC][IAS] Add definitions for OSA 2011 instructions
Reviewers: rorth, brad0, s-barannikov
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/138403
Added:
llvm/test/MC/Sparc/sparc-osa2011.s
llvm/test/MC/Sparc/sparc64-branch-offset.s
Modified:
llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h
llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
llvm/lib/Target/Sparc/Sparc.td
llvm/lib/Target/Sparc/SparcInstrAliases.td
llvm/lib/Target/Sparc/SparcInstrFormats.td
llvm/lib/Target/Sparc/SparcInstrInfo.td
llvm/lib/Target/Sparc/SparcInstrUAOSA.td
llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
llvm/test/MC/Sparc/Relocations/expr.s
Removed:
llvm/test/MC/Sparc/sparc64-bpr-offset.s
################################################################################
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index 1a2d679b4ac10..173fe3df0d95a 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -261,6 +261,8 @@ DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);
+static DecodeStatus DecodeSIMM5(MCInst &Inst, unsigned insn, uint64_t Address,
+ const MCDisassembler *Decoder);
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);
template <unsigned N>
@@ -336,6 +338,13 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSIMM5(MCInst &MI, unsigned insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ assert(isUInt<5>(insn));
+ MI.addOperand(MCOperand::createImm(SignExtend64<5>(insn)));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder) {
assert(isUInt<13>(insn));
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
index 95b78e0905b6d..0e29d17021504 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
@@ -50,6 +50,18 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
return (d16hi << 20) | d16lo;
}
+ case ELF::R_SPARC_WDISP10: {
+ // FIXME this really should be an error reporting check.
+ assert((Value & 0x3) == 0);
+
+ // 7.17 Compare and Branch
+ // Inst{20-19} = d10hi;
+ // Inst{12-5} = d10lo;
+ unsigned d10hi = (Value >> 10) & 0x3;
+ unsigned d10lo = (Value >> 2) & 0xff;
+ return (d10hi << 19) | (d10lo << 5);
+ }
+
case ELF::R_SPARC_HIX22:
return (~Value >> 10) & 0x3fffff;
@@ -61,6 +73,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
case Sparc::fixup_sparc_13:
return Value & 0x1fff;
+ case ELF::R_SPARC_5:
+ return Value & 0x1f;
+
case ELF::R_SPARC_LOX10:
return (Value & 0x3ff) | 0x1c00;
@@ -163,6 +178,9 @@ namespace {
case ELF::R_SPARC_PC22:
Info = {"", 10, 22, MCFixupKindInfo::FKF_IsPCRel};
break;
+ case ELF::R_SPARC_WDISP10:
+ Info = {"", 0, 32, MCFixupKindInfo::FKF_IsPCRel};
+ break;
case ELF::R_SPARC_WDISP16:
Info = {"", 0, 32, MCFixupKindInfo::FKF_IsPCRel};
break;
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h
index 1c8e64dd7d16d..222fa5f3dca78 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h
@@ -11,6 +11,7 @@
#include "llvm/MC/MCFixup.h"
+// clang-format off
namespace llvm {
namespace Sparc {
// clang-format off
@@ -28,5 +29,5 @@ namespace llvm {
// clang-format on
}
}
-
+// clang-format on
#endif
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
index 99af8194450e3..2c8dbaa5aba60 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
@@ -72,6 +72,9 @@ class SparcMCCodeEmitter : public MCCodeEmitter {
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ unsigned getSImm5OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
@@ -81,6 +84,9 @@ class SparcMCCodeEmitter : public MCCodeEmitter {
unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ unsigned getCompareAndBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
@@ -141,6 +147,31 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
return 0;
}
+unsigned SparcMCCodeEmitter::getSImm5OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+
+ if (MO.isImm())
+ return MO.getImm();
+
+ assert(MO.isExpr() &&
+ "getSImm5OpValue expects only expressions or an immediate");
+
+ const MCExpr *Expr = MO.getExpr();
+
+ // Constant value, no fixup is needed
+ if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
+ return CE->getValue();
+
+ if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
+ Fixups.push_back(MCFixup::create(0, Expr, SExpr->getFixupKind()));
+ return 0;
+ }
+ Fixups.push_back(MCFixup::create(0, Expr, ELF::R_SPARC_5));
+ return 0;
+}
+
unsigned
SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
@@ -217,6 +248,18 @@ unsigned SparcMCCodeEmitter::getBranchOnRegTargetOpValue(
return 0;
}
+unsigned SparcMCCodeEmitter::getCompareAndBranchTargetOpValue(
+ const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ if (MO.isImm())
+ return getMachineOpValue(MI, MO, Fixups, STI);
+
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP10));
+
+ return 0;
+}
+
#include "SparcGenMCCodeEmitter.inc"
MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 93c3098bd89fe..6e6c887e60e12 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -55,6 +55,9 @@ def FeatureUA2005
def FeatureUA2007
: SubtargetFeature<"ua2007", "IsUA2007", "true",
"Enable UltraSPARC Architecture 2007 extensions">;
+def FeatureOSA2011
+ : SubtargetFeature<"osa2011", "IsOSA2011", "true",
+ "Enable Oracle SPARC Architecture 2011 extensions">;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
@@ -166,7 +169,7 @@ def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureUA2005, FeatureUA2007]>;
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
- FeatureUA2005, FeatureUA2007]>;
+ FeatureUA2005, FeatureUA2007, FeatureOSA2011]>;
// LEON 2 FT generic
def : Processor<"leon2", LEON2Itineraries,
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index 590395c16965b..459fd193db0ed 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -331,6 +331,25 @@ multiclass reg_cond_alias<string rcond, int condVal> {
Requires<[Is64Bit]>;
}
+// Instruction aliases for compare-and-branch.
+multiclass cwb_cond_alias<string cond, int condVal> {
+ def : InstAlias<"cwb" # cond # " $rs1, $rs2, $imm",
+ (CWBCONDrr cbtarget:$imm, condVal, IntRegs:$rs1, IntRegs:$rs2)>,
+ Requires<[HasOSA2011]>;
+ def : InstAlias<"cwb" # cond # " $rs1, $simm5, $imm",
+ (CWBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,
+ Requires<[HasOSA2011]>;
+}
+
+multiclass cxb_cond_alias<string cond, int condVal> {
+ def : InstAlias<"cxb" # cond # " $rs1, $rs2, $imm",
+ (CXBCONDrr cbtarget:$imm, condVal, IntRegs:$rs1, IntRegs:$rs2)>,
+ Requires<[HasOSA2011]>;
+ def : InstAlias<"cxb" # cond # " $rs1, $simm5, $imm",
+ (CXBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,
+ Requires<[HasOSA2011]>;
+}
+
defm : int_cond_alias<"a", 0b1000>;
defm : int_cond_alias<"n", 0b0000>;
defm : int_cond_alias<"ne", 0b1001>;
@@ -408,6 +427,44 @@ defm : reg_cond_alias<"ne", 0b101>;
defm : reg_cond_alias<"gz", 0b110>;
defm : reg_cond_alias<"gez", 0b111>;
+defm : cwb_cond_alias<"ne", 0b1001>;
+defm : cwb_cond_alias<"e", 0b0001>;
+defm : cwb_cond_alias<"g", 0b1010>;
+defm : cwb_cond_alias<"le", 0b0010>;
+defm : cwb_cond_alias<"ge", 0b1011>;
+defm : cwb_cond_alias<"l", 0b0011>;
+defm : cwb_cond_alias<"gu", 0b1100>;
+defm : cwb_cond_alias<"leu", 0b0100>;
+defm : cwb_cond_alias<"cc", 0b1101>;
+defm : cwb_cond_alias<"cs", 0b0101>;
+defm : cwb_cond_alias<"pos", 0b1110>;
+defm : cwb_cond_alias<"neg", 0b0110>;
+defm : cwb_cond_alias<"vc", 0b1111>;
+defm : cwb_cond_alias<"vs", 0b0111>;
+let EmitPriority = 0 in {
+ defm : cwb_cond_alias<"geu", 0b1101>; // same as cc
+ defm : cwb_cond_alias<"lu", 0b0101>; // same as cs
+}
+
+defm : cxb_cond_alias<"ne", 0b1001>;
+defm : cxb_cond_alias<"e", 0b0001>;
+defm : cxb_cond_alias<"g", 0b1010>;
+defm : cxb_cond_alias<"le", 0b0010>;
+defm : cxb_cond_alias<"ge", 0b1011>;
+defm : cxb_cond_alias<"l", 0b0011>;
+defm : cxb_cond_alias<"gu", 0b1100>;
+defm : cxb_cond_alias<"leu", 0b0100>;
+defm : cxb_cond_alias<"cc", 0b1101>;
+defm : cxb_cond_alias<"cs", 0b0101>;
+defm : cxb_cond_alias<"pos", 0b1110>;
+defm : cxb_cond_alias<"neg", 0b0110>;
+defm : cxb_cond_alias<"vc", 0b1111>;
+defm : cxb_cond_alias<"vs", 0b0111>;
+let EmitPriority = 0 in {
+ defm : cxb_cond_alias<"geu", 0b1101>; // same as cc
+ defm : cxb_cond_alias<"lu", 0b0101>; // same as cs
+}
+
// Section A.3 Synthetic Instructions
// Most are marked as Emit=0, so that they are not used for disassembly. This is
@@ -665,3 +722,9 @@ def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Re
// sir -> sir 0
def : InstAlias<"sir", (SIR 0), 0>;
+
+// pause reg_or_imm -> wrasr %g0, reg_or_imm, %asr27
+let Predicates = [HasOSA2011] in {
+ def : InstAlias<"pause $rs2", (WRASRrr ASR27, G0, IntRegs:$rs2), 1>;
+ def : InstAlias<"pause $simm13", (WRASRri ASR27, G0, simm13Op:$simm13), 1>;
+} // Predicates = [HasOSA2011]
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 2998f53ef2dbc..79c4cb2128a0f 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -102,6 +102,49 @@ class F2_4<bit annul, bit pred, dag outs, dag ins,
let Inst{13-0} = imm16{13-0};
}
+class F2_5<bit cc, dag outs, dag ins, string asmstr,
+ list<dag> pattern = [], InstrItinClass itin = NoItinerary>
+ : InstSP<outs, ins, asmstr, pattern, itin> {
+ bits<10> imm10;
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<4> cond;
+
+ let op = 0; // op = 0
+
+ let Inst{29} = cond{3};
+ let Inst{28} = 1;
+ let Inst{27-25} = cond{2-0};
+ let Inst{24-22} = 0b011;
+ let Inst{21} = cc;
+ let Inst{20-19} = imm10{9-8};
+ let Inst{18-14} = rs1;
+ let Inst{13} = 0; // i = 0
+ let Inst{12-5} = imm10{7-0};
+ let Inst{4-0} = rs2;
+}
+
+class F2_6<bit cc, dag outs, dag ins, string asmstr,
+ list<dag> pattern = [], InstrItinClass itin = NoItinerary>
+ : InstSP<outs, ins, asmstr, pattern, itin> {
+ bits<10> imm10;
+ bits<5> rs1;
+ bits<5> simm5;
+ bits<4> cond;
+
+ let op = 0; // op = 0
+
+ let Inst{29} = cond{3};
+ let Inst{28} = 1;
+ let Inst{27-25} = cond{2-0};
+ let Inst{24-22} = 0b011;
+ let Inst{21} = cc;
+ let Inst{20-19} = imm10{9-8};
+ let Inst{18-14} = rs1;
+ let Inst{13} = 1; // i = 1
+ let Inst{12-5} = imm10{7-0};
+ let Inst{4-0} = simm5;
+}
//===----------------------------------------------------------------------===//
// Format #3 instruction classes in the Sparc
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 21379950485e6..074a04a5dd747 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -55,6 +55,10 @@ def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
def HasUA2007 : Predicate<"Subtarget->isUA2007()">,
AssemblerPredicate<(all_of FeatureUA2007)>;
+// HasOSA2011 - This is true when the target processor has OSA 2011 extensions.
+def HasOSA2011 : Predicate<"Subtarget->isOSA2011()">,
+ AssemblerPredicate<(all_of FeatureOSA2011)>;
+
// HasHardQuad - This is true when the target processor supports quad floating
// point instructions.
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
@@ -93,6 +97,8 @@ def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
// FIXME these should have AsmOperandClass.
def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;
+def simm5 : PatLeaf<(imm), [{ return isInt<5>(N->getSExtValue()); }]>;
+
def simm10 : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;
def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
@@ -153,6 +159,12 @@ def SparcMEMriAsmOperand : AsmOperandClass {
let ParserMethod = "parseMEMOperand";
}
+def simm5Op : Operand<iPTR> {
+ let OperandType = "OPERAND_IMMEDIATE";
+ let DecoderMethod = "DecodeSIMM5";
+ let EncoderMethod = "getSImm5OpValue";
+}
+
def simm13Op : Operand<iPTR> {
let OperandType = "OPERAND_IMMEDIATE";
let DecoderMethod = "DecodeSIMM13";
@@ -246,6 +258,13 @@ def bprtarget16 : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
}
+def cbtarget : Operand<OtherVT> {
+ let EncoderMethod = "getCompareAndBranchTargetOpValue";
+ let DecoderMethod = "DecodeDisp<10>";
+ let PrintMethod = "printCTILabel";
+ let OperandType = "OPERAND_PCREL";
+}
+
def SparcCallTargetAsmOperand : AsmOperandClass {
let Name = "CallTarget";
let ParserMethod = "parseCallTarget";
diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
index 1e1a054f69a41..3a30e552e6db1 100644
--- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
+++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//
// This file contains instruction formats, definitions and patterns needed for
-// UA 2005 and UA 2007 instructions on SPARC.
+// UA 2005, UA 2007, and OSA 2011 instructions on SPARC.
//===----------------------------------------------------------------------===//
class UA2005RegWin<string asmstr, bits<5> fcn>
@@ -23,6 +23,16 @@ class FourOp<string OpcStr, bits<6> op3val, bits<4> op5val,
: F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3),
!strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;
+/// F2_56 multiclass - Define a F2_5/F2_6 pattern in one shot.
+multiclass F2_56<string OpcStr, bits<1> cc> {
+ def rr : F2_5<cc, (outs),
+ (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, IntRegs:$rs2),
+ !strconcat(OpcStr, "$cond $rs1, $rs2, $imm10")>;
+ def ri : F2_6<cc, (outs),
+ (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, simm5Op:$simm5),
+ !strconcat(OpcStr, "$cond $rs1, $simm5, $imm10")>;
+}
+
// UltraSPARC Architecture 2005 Instructions
let Predicates = [HasUA2005] in {
let hasSideEffects = 1 in {
@@ -45,3 +55,14 @@ def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;
} // Predicates = [HasUA2007]
+
+// Oracle SPARC Architecture 2011 Instructions
+let Predicates = [HasOSA2011] in {
+let isBranch = 1, isTerminator = 1, hasDelaySlot = 0 in {
+defm CWBCOND : F2_56<"cwb", 0>;
+defm CXBCOND : F2_56<"cxb", 1>;
+}
+
+def FPMADDX : FourOp<"fpmaddx", 0b110111, 0b0000, DFPRegs>;
+def FPMADDXHI : FourOp<"fpmaddxhi", 0b110111, 0b0100, DFPRegs>;
+} // Predicates = [HasOSA2011]
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
index bc32e7dbb3980..f54bae71661a3 100644
--- a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005,+ua2007 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005,+ua2007,+osa2011 | FileCheck %s
## UA 2005 instructions.
@@ -29,3 +29,126 @@
0x8f,0xb8,0x4b,0x23
# CHECK: fnmsubd %f0, %f2, %f4, %f6
0x8d,0xb8,0x09,0x42
+
+## OSA 2011 instructions.
+
+# CHECK: cwbne %o0, %o1, .+0
+0x32,0xc2,0x00,0x09
+# CHECK: cwbe %o0, %o1, .+0
+0x12,0xc2,0x00,0x09
+# CHECK: cwbg %o0, %o1, .+0
+0x34,0xc2,0x00,0x09
+# CHECK: cwble %o0, %o1, .+0
+0x14,0xc2,0x00,0x09
+# CHECK: cwbge %o0, %o1, .+0
+0x36,0xc2,0x00,0x09
+# CHECK: cwbl %o0, %o1, .+0
+0x16,0xc2,0x00,0x09
+# CHECK: cwbgu %o0, %o1, .+0
+0x38,0xc2,0x00,0x09
+# CHECK: cwbleu %o0, %o1, .+0
+0x18,0xc2,0x00,0x09
+# CHECK: cwbcc %o0, %o1, .+0
+0x3a,0xc2,0x00,0x09
+# CHECK: cwbcs %o0, %o1, .+0
+0x1a,0xc2,0x00,0x09
+# CHECK: cwbpos %o0, %o1, .+0
+0x3c,0xc2,0x00,0x09
+# CHECK: cwbneg %o0, %o1, .+0
+0x1c,0xc2,0x00,0x09
+# CHECK: cwbvc %o0, %o1, .+0
+0x3e,0xc2,0x00,0x09
+# CHECK: cwbvs %o0, %o1, .+0
+0x1e,0xc2,0x00,0x09
+# CHECK: cxbne %o0, %o1, .+0
+0x32,0xe2,0x00,0x09
+# CHECK: cxbe %o0, %o1, .+0
+0x12,0xe2,0x00,0x09
+# CHECK: cxbg %o0, %o1, .+0
+0x34,0xe2,0x00,0x09
+# CHECK: cxble %o0, %o1, .+0
+0x14,0xe2,0x00,0x09
+# CHECK: cxbge %o0, %o1, .+0
+0x36,0xe2,0x00,0x09
+# CHECK: cxbl %o0, %o1, .+0
+0x16,0xe2,0x00,0x09
+# CHECK: cxbgu %o0, %o1, .+0
+0x38,0xe2,0x00,0x09
+# CHECK: cxbleu %o0, %o1, .+0
+0x18,0xe2,0x00,0x09
+# CHECK: cxbcc %o0, %o1, .+0
+0x3a,0xe2,0x00,0x09
+# CHECK: cxbcs %o0, %o1, .+0
+0x1a,0xe2,0x00,0x09
+# CHECK: cxbpos %o0, %o1, .+0
+0x3c,0xe2,0x00,0x09
+# CHECK: cxbneg %o0, %o1, .+0
+0x1c,0xe2,0x00,0x09
+# CHECK: cxbvc %o0, %o1, .+0
+0x3e,0xe2,0x00,0x09
+# CHECK: cxbvs %o0, %o1, .+0
+0x1e,0xe2,0x00,0x09
+# CHECK: cwbne %o0, 1, .+0
+0x32,0xc2,0x20,0x01
+# CHECK: cwbe %o0, 1, .+0
+0x12,0xc2,0x20,0x01
+# CHECK: cwbg %o0, 1, .+0
+0x34,0xc2,0x20,0x01
+# CHECK: cwble %o0, 1, .+0
+0x14,0xc2,0x20,0x01
+# CHECK: cwbge %o0, 1, .+0
+0x36,0xc2,0x20,0x01
+# CHECK: cwbl %o0, 1, .+0
+0x16,0xc2,0x20,0x01
+# CHECK: cwbgu %o0, 1, .+0
+0x38,0xc2,0x20,0x01
+# CHECK: cwbleu %o0, 1, .+0
+0x18,0xc2,0x20,0x01
+# CHECK: cwbcc %o0, 1, .+0
+0x3a,0xc2,0x20,0x01
+# CHECK: cwbcs %o0, 1, .+0
+0x1a,0xc2,0x20,0x01
+# CHECK: cwbpos %o0, 1, .+0
+0x3c,0xc2,0x20,0x01
+# CHECK: cwbneg %o0, 1, .+0
+0x1c,0xc2,0x20,0x01
+# CHECK: cwbvc %o0, 1, .+0
+0x3e,0xc2,0x20,0x01
+# CHECK: cwbvs %o0, 1, .+0
+0x1e,0xc2,0x20,0x01
+# CHECK: cxbne %o0, 1, .+0
+0x32,0xe2,0x20,0x01
+# CHECK: cxbe %o0, 1, .+0
+0x12,0xe2,0x20,0x01
+# CHECK: cxbg %o0, 1, .+0
+0x34,0xe2,0x20,0x01
+# CHECK: cxble %o0, 1, .+0
+0x14,0xe2,0x20,0x01
+# CHECK: cxbge %o0, 1, .+0
+0x36,0xe2,0x20,0x01
+# CHECK: cxbl %o0, 1, .+0
+0x16,0xe2,0x20,0x01
+# CHECK: cxbgu %o0, 1, .+0
+0x38,0xe2,0x20,0x01
+# CHECK: cxbleu %o0, 1, .+0
+0x18,0xe2,0x20,0x01
+# CHECK: cxbcc %o0, 1, .+0
+0x3a,0xe2,0x20,0x01
+# CHECK: cxbcs %o0, 1, .+0
+0x1a,0xe2,0x20,0x01
+# CHECK: cxbpos %o0, 1, .+0
+0x3c,0xe2,0x20,0x01
+# CHECK: cxbneg %o0, 1, .+0
+0x1c,0xe2,0x20,0x01
+# CHECK: cxbvc %o0, 1, .+0
+0x3e,0xe2,0x20,0x01
+# CHECK: cxbvs %o0, 1, .+0
+0x1e,0xe2,0x20,0x01
+# CHECK: fpmaddx %f0, %f2, %f4, %f6
+0x8d,0xb8,0x08,0x02
+# CHECK: fpmaddxhi %f0, %f2, %f4, %f6
+0x8d,0xb8,0x08,0x82
+# CHECK: pause %o5
+0xb7,0x80,0x00,0x0d
+# CHECK: pause 5
+0xb7,0x80,0x20,0x05
diff --git a/llvm/test/MC/Sparc/Relocations/expr.s b/llvm/test/MC/Sparc/Relocations/expr.s
index fcde7d6a1d905..ec3a3ac699b6b 100644
--- a/llvm/test/MC/Sparc/Relocations/expr.s
+++ b/llvm/test/MC/Sparc/Relocations/expr.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -triple=sparc | FileCheck %s
-! RUN: llvm-mc %s -triple=sparc -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP
+! RUN: llvm-mc %s -triple=sparc -mattr=+osa2011 | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -mattr=+osa2011 -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP
! CHECK: mov 1033, %o1
mov (0x400|9), %o1
@@ -12,7 +12,7 @@ symStart:
b symStart + 4
! CHECK: mov symEnd-symStart, %g1
- ! OBJDUMP: mov 0x18, %g1
+ ! OBJDUMP: mov 0x20, %g1
mov symEnd - symStart, %g1
! CHECK: sethi %hi(sym+10), %g2
@@ -30,10 +30,18 @@ symStart:
! CHECK: add %g1, 100+val, %g2
! OBJDUMP: R_SPARC_13 val+0x64
add %g1, 100 + val, %g2
+
+ ! CHECK: cwbe %g0, val+2, symStart
+ ! OBJDUMP: R_SPARC_5 val+0x2
+ cwbe %g0, val + 2, symStart
+
+ ! CHECK: cxbe %g0, val+2, symStart
+ ! OBJDUMP: R_SPARC_5 val+0x2
+ cxbe %g0, val + 2, symStart
symEnd:
! "." is exactly like a temporary symbol equated to the current line.
-! RUN: llvm-mc %s -triple=sparc | FileCheck %s --check-prefix=DOTEXPR
+! RUN: llvm-mc %s -triple=sparc -mattr=+osa2011 | FileCheck %s --check-prefix=DOTEXPR
! DOTEXPR: .Ltmp0
! DOTEXPR-NEXT: ba .Ltmp0+8
diff --git a/llvm/test/MC/Sparc/sparc-osa2011.s b/llvm/test/MC/Sparc/sparc-osa2011.s
new file mode 100644
index 0000000000000..af3723d814850
--- /dev/null
+++ b/llvm/test/MC/Sparc/sparc-osa2011.s
@@ -0,0 +1,190 @@
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-OSA2011 --implicit-check-not=error:
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+osa2011 -show-encoding | FileCheck %s --check-prefixes=OSA2011
+
+!! OSA 2011 instructions.
+
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbne %o0, %o1, .BB0 ! encoding: [0x32'A',0xc2'A',A,0x09'A']
+cwbne %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbe %o0, %o1, .BB0 ! encoding: [0x12'A',0xc2'A',A,0x09'A']
+cwbe %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbg %o0, %o1, .BB0 ! encoding: [0x34'A',0xc2'A',A,0x09'A']
+cwbg %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwble %o0, %o1, .BB0 ! encoding: [0x14'A',0xc2'A',A,0x09'A']
+cwble %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbge %o0, %o1, .BB0 ! encoding: [0x36'A',0xc2'A',A,0x09'A']
+cwbge %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbl %o0, %o1, .BB0 ! encoding: [0x16'A',0xc2'A',A,0x09'A']
+cwbl %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbgu %o0, %o1, .BB0 ! encoding: [0x38'A',0xc2'A',A,0x09'A']
+cwbgu %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbleu %o0, %o1, .BB0 ! encoding: [0x18'A',0xc2'A',A,0x09'A']
+cwbleu %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbcc %o0, %o1, .BB0 ! encoding: [0x3a'A',0xc2'A',A,0x09'A']
+cwbcc %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbcs %o0, %o1, .BB0 ! encoding: [0x1a'A',0xc2'A',A,0x09'A']
+cwbcs %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbpos %o0, %o1, .BB0 ! encoding: [0x3c'A',0xc2'A',A,0x09'A']
+cwbpos %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbneg %o0, %o1, .BB0 ! encoding: [0x1c'A',0xc2'A',A,0x09'A']
+cwbneg %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbvc %o0, %o1, .BB0 ! encoding: [0x3e'A',0xc2'A',A,0x09'A']
+cwbvc %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbvs %o0, %o1, .BB0 ! encoding: [0x1e'A',0xc2'A',A,0x09'A']
+cwbvs %o0, %o1, .BB0
+
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbne %o0, %o1, .BB0 ! encoding: [0x32'A',0xe2'A',A,0x09'A']
+cxbne %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbe %o0, %o1, .BB0 ! encoding: [0x12'A',0xe2'A',A,0x09'A']
+cxbe %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbg %o0, %o1, .BB0 ! encoding: [0x34'A',0xe2'A',A,0x09'A']
+cxbg %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxble %o0, %o1, .BB0 ! encoding: [0x14'A',0xe2'A',A,0x09'A']
+cxble %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbge %o0, %o1, .BB0 ! encoding: [0x36'A',0xe2'A',A,0x09'A']
+cxbge %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbl %o0, %o1, .BB0 ! encoding: [0x16'A',0xe2'A',A,0x09'A']
+cxbl %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbgu %o0, %o1, .BB0 ! encoding: [0x38'A',0xe2'A',A,0x09'A']
+cxbgu %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbleu %o0, %o1, .BB0 ! encoding: [0x18'A',0xe2'A',A,0x09'A']
+cxbleu %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbcc %o0, %o1, .BB0 ! encoding: [0x3a'A',0xe2'A',A,0x09'A']
+cxbcc %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbcs %o0, %o1, .BB0 ! encoding: [0x1a'A',0xe2'A',A,0x09'A']
+cxbcs %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbpos %o0, %o1, .BB0 ! encoding: [0x3c'A',0xe2'A',A,0x09'A']
+cxbpos %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbneg %o0, %o1, .BB0 ! encoding: [0x1c'A',0xe2'A',A,0x09'A']
+cxbneg %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbvc %o0, %o1, .BB0 ! encoding: [0x3e'A',0xe2'A',A,0x09'A']
+cxbvc %o0, %o1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbvs %o0, %o1, .BB0 ! encoding: [0x1e'A',0xe2'A',A,0x09'A']
+cxbvs %o0, %o1, .BB0
+
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbne %o0, 1, .BB0 ! encoding: [0x32'A',0xc2'A',0x20'A',0x01'A']
+cwbne %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbe %o0, 1, .BB0 ! encoding: [0x12'A',0xc2'A',0x20'A',0x01'A']
+cwbe %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbg %o0, 1, .BB0 ! encoding: [0x34'A',0xc2'A',0x20'A',0x01'A']
+cwbg %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwble %o0, 1, .BB0 ! encoding: [0x14'A',0xc2'A',0x20'A',0x01'A']
+cwble %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbge %o0, 1, .BB0 ! encoding: [0x36'A',0xc2'A',0x20'A',0x01'A']
+cwbge %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbl %o0, 1, .BB0 ! encoding: [0x16'A',0xc2'A',0x20'A',0x01'A']
+cwbl %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbgu %o0, 1, .BB0 ! encoding: [0x38'A',0xc2'A',0x20'A',0x01'A']
+cwbgu %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbleu %o0, 1, .BB0 ! encoding: [0x18'A',0xc2'A',0x20'A',0x01'A']
+cwbleu %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbcc %o0, 1, .BB0 ! encoding: [0x3a'A',0xc2'A',0x20'A',0x01'A']
+cwbcc %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbcs %o0, 1, .BB0 ! encoding: [0x1a'A',0xc2'A',0x20'A',0x01'A']
+cwbcs %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbpos %o0, 1, .BB0 ! encoding: [0x3c'A',0xc2'A',0x20'A',0x01'A']
+cwbpos %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbneg %o0, 1, .BB0 ! encoding: [0x1c'A',0xc2'A',0x20'A',0x01'A']
+cwbneg %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbvc %o0, 1, .BB0 ! encoding: [0x3e'A',0xc2'A',0x20'A',0x01'A']
+cwbvc %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cwbvs %o0, 1, .BB0 ! encoding: [0x1e'A',0xc2'A',0x20'A',0x01'A']
+cwbvs %o0, 1, .BB0
+
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbne %o0, 1, .BB0 ! encoding: [0x32'A',0xe2'A',0x20'A',0x01'A']
+cxbne %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbe %o0, 1, .BB0 ! encoding: [0x12'A',0xe2'A',0x20'A',0x01'A']
+cxbe %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbg %o0, 1, .BB0 ! encoding: [0x34'A',0xe2'A',0x20'A',0x01'A']
+cxbg %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxble %o0, 1, .BB0 ! encoding: [0x14'A',0xe2'A',0x20'A',0x01'A']
+cxble %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbge %o0, 1, .BB0 ! encoding: [0x36'A',0xe2'A',0x20'A',0x01'A']
+cxbge %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbl %o0, 1, .BB0 ! encoding: [0x16'A',0xe2'A',0x20'A',0x01'A']
+cxbl %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbgu %o0, 1, .BB0 ! encoding: [0x38'A',0xe2'A',0x20'A',0x01'A']
+cxbgu %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbleu %o0, 1, .BB0 ! encoding: [0x18'A',0xe2'A',0x20'A',0x01'A']
+cxbleu %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbcc %o0, 1, .BB0 ! encoding: [0x3a'A',0xe2'A',0x20'A',0x01'A']
+cxbcc %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbcs %o0, 1, .BB0 ! encoding: [0x1a'A',0xe2'A',0x20'A',0x01'A']
+cxbcs %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbpos %o0, 1, .BB0 ! encoding: [0x3c'A',0xe2'A',0x20'A',0x01'A']
+cxbpos %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbneg %o0, 1, .BB0 ! encoding: [0x1c'A',0xe2'A',0x20'A',0x01'A']
+cxbneg %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbvc %o0, 1, .BB0 ! encoding: [0x3e'A',0xe2'A',0x20'A',0x01'A']
+cxbvc %o0, 1, .BB0
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: cxbvs %o0, 1, .BB0 ! encoding: [0x1e'A',0xe2'A',0x20'A',0x01'A']
+cxbvs %o0, 1, .BB0
+
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: fpmaddx %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0x02]
+fpmaddx %f0, %f2, %f4, %f6
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: fpmaddxhi %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0x82]
+fpmaddxhi %f0, %f2, %f4, %f6
+
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: pause %o5 ! encoding: [0xb7,0x80,0x00,0x0d]
+pause %o5
+! NO-OSA2011: error: instruction requires a CPU feature not currently enabled
+! OSA2011: pause 5 ! encoding: [0xb7,0x80,0x20,0x05]
+pause 5
diff --git a/llvm/test/MC/Sparc/sparc64-bpr-offset.s b/llvm/test/MC/Sparc/sparc64-bpr-offset.s
deleted file mode 100644
index 3abae6a5b5710..0000000000000
--- a/llvm/test/MC/Sparc/sparc64-bpr-offset.s
+++ /dev/null
@@ -1,31 +0,0 @@
-! RUN: llvm-mc -triple=sparcv9 -filetype=obj %s | llvm-objdump -d --no-print-imm-hex - | FileCheck %s --check-prefix=BIN
-
- !! SPARCv9/SPARC64 BPr branches have
diff erent offset encoding from the others,
- !! make sure that our offset bits don't trample on other fields.
- !! This is particularly important with backwards branches.
-
- ! BIN: 0: 02 c8 40 01 brz %g1, 0x4
- ! BIN: 4: 04 c8 40 01 brlez %g1, 0x8
- ! BIN: 8: 06 c8 40 01 brlz %g1, 0xc
- ! BIN: c: 0a c8 40 01 brnz %g1, 0x10
- ! BIN: 10: 0c c8 40 01 brgz %g1, 0x14
- ! BIN: 14: 0e c8 40 01 brgez %g1, 0x18
- brz %g1, .+4
- brlez %g1, .+4
- brlz %g1, .+4
- brnz %g1, .+4
- brgz %g1, .+4
- brgez %g1, .+4
-
- ! BIN: 18: 02 f8 7f ff brz %g1, 0x14
- ! BIN: 1c: 04 f8 7f ff brlez %g1, 0x18
- ! BIN: 20: 06 f8 7f ff brlz %g1, 0x1c
- ! BIN: 24: 0a f8 7f ff brnz %g1, 0x20
- ! BIN: 28: 0c f8 7f ff brgz %g1, 0x24
- ! BIN: 2c: 0e f8 7f ff brgez %g1, 0x28
- brz %g1, .-4
- brlez %g1, .-4
- brlz %g1, .-4
- brnz %g1, .-4
- brgz %g1, .-4
- brgez %g1, .-4
diff --git a/llvm/test/MC/Sparc/sparc64-branch-offset.s b/llvm/test/MC/Sparc/sparc64-branch-offset.s
new file mode 100644
index 0000000000000..c0be339bec728
--- /dev/null
+++ b/llvm/test/MC/Sparc/sparc64-branch-offset.s
@@ -0,0 +1,267 @@
+! RUN: llvm-mc -triple=sparcv9 -mattr=+osa2011 -filetype=obj %s | llvm-objdump --mattr=+osa2011 --no-print-imm-hex -d - | FileCheck %s --check-prefix=BIN
+
+!! SPARCv9/SPARC64 BPr branches have
diff erent offset encoding from the others,
+!! make sure that our offset bits don't trample on other fields.
+!! This is particularly important with backwards branches.
+
+! BIN: 0: 02 c8 40 01 brz %g1, 0x4
+! BIN: 4: 04 c8 40 01 brlez %g1, 0x8
+! BIN: 8: 06 c8 40 01 brlz %g1, 0xc
+! BIN: c: 0a c8 40 01 brnz %g1, 0x10
+! BIN: 10: 0c c8 40 01 brgz %g1, 0x14
+! BIN: 14: 0e c8 40 01 brgez %g1, 0x18
+brz %g1, .+4
+brlez %g1, .+4
+brlz %g1, .+4
+brnz %g1, .+4
+brgz %g1, .+4
+brgez %g1, .+4
+
+! BIN: 18: 02 f8 7f ff brz %g1, 0x14
+! BIN: 1c: 04 f8 7f ff brlez %g1, 0x18
+! BIN: 20: 06 f8 7f ff brlz %g1, 0x1c
+! BIN: 24: 0a f8 7f ff brnz %g1, 0x20
+! BIN: 28: 0c f8 7f ff brgz %g1, 0x24
+! BIN: 2c: 0e f8 7f ff brgez %g1, 0x28
+brz %g1, .-4
+brlez %g1, .-4
+brlz %g1, .-4
+brnz %g1, .-4
+brgz %g1, .-4
+brgez %g1, .-4
+
+!! Similarly, OSA2011 CBCond branches have
diff erent offset encoding,
+!! make sure that our offset bits don't trample on other fields.
+!! This is particularly important with backwards branches.
+
+!BIN: 30: 32 c2 00 29 cwbne %o0, %o1, 0x34
+!BIN: 34: 12 c2 00 29 cwbe %o0, %o1, 0x38
+!BIN: 38: 34 c2 00 29 cwbg %o0, %o1, 0x3c
+!BIN: 3c: 14 c2 00 29 cwble %o0, %o1, 0x40
+!BIN: 40: 36 c2 00 29 cwbge %o0, %o1, 0x44
+!BIN: 44: 16 c2 00 29 cwbl %o0, %o1, 0x48
+!BIN: 48: 38 c2 00 29 cwbgu %o0, %o1, 0x4c
+!BIN: 4c: 18 c2 00 29 cwbleu %o0, %o1, 0x50
+!BIN: 50: 3a c2 00 29 cwbcc %o0, %o1, 0x54
+!BIN: 54: 1a c2 00 29 cwbcs %o0, %o1, 0x58
+!BIN: 58: 3c c2 00 29 cwbpos %o0, %o1, 0x5c
+!BIN: 5c: 1c c2 00 29 cwbneg %o0, %o1, 0x60
+!BIN: 60: 3e c2 00 29 cwbvc %o0, %o1, 0x64
+!BIN: 64: 1e c2 00 29 cwbvs %o0, %o1, 0x68
+cwbne %o0, %o1, .+4
+cwbe %o0, %o1, .+4
+cwbg %o0, %o1, .+4
+cwble %o0, %o1, .+4
+cwbge %o0, %o1, .+4
+cwbl %o0, %o1, .+4
+cwbgu %o0, %o1, .+4
+cwbleu %o0, %o1, .+4
+cwbcc %o0, %o1, .+4
+cwbcs %o0, %o1, .+4
+cwbpos %o0, %o1, .+4
+cwbneg %o0, %o1, .+4
+cwbvc %o0, %o1, .+4
+cwbvs %o0, %o1, .+4
+
+!BIN: 68: 32 da 1f e9 cwbne %o0, %o1, 0x64
+!BIN: 6c: 12 da 1f e9 cwbe %o0, %o1, 0x68
+!BIN: 70: 34 da 1f e9 cwbg %o0, %o1, 0x6c
+!BIN: 74: 14 da 1f e9 cwble %o0, %o1, 0x70
+!BIN: 78: 36 da 1f e9 cwbge %o0, %o1, 0x74
+!BIN: 7c: 16 da 1f e9 cwbl %o0, %o1, 0x78
+!BIN: 80: 38 da 1f e9 cwbgu %o0, %o1, 0x7c
+!BIN: 84: 18 da 1f e9 cwbleu %o0, %o1, 0x80
+!BIN: 88: 3a da 1f e9 cwbcc %o0, %o1, 0x84
+!BIN: 8c: 1a da 1f e9 cwbcs %o0, %o1, 0x88
+!BIN: 90: 3c da 1f e9 cwbpos %o0, %o1, 0x8c
+!BIN: 94: 1c da 1f e9 cwbneg %o0, %o1, 0x90
+!BIN: 98: 3e da 1f e9 cwbvc %o0, %o1, 0x94
+!BIN: 9c: 1e da 1f e9 cwbvs %o0, %o1, 0x98
+cwbne %o0, %o1, .-4
+cwbe %o0, %o1, .-4
+cwbg %o0, %o1, .-4
+cwble %o0, %o1, .-4
+cwbge %o0, %o1, .-4
+cwbl %o0, %o1, .-4
+cwbgu %o0, %o1, .-4
+cwbleu %o0, %o1, .-4
+cwbcc %o0, %o1, .-4
+cwbcs %o0, %o1, .-4
+cwbpos %o0, %o1, .-4
+cwbneg %o0, %o1, .-4
+cwbvc %o0, %o1, .-4
+cwbvs %o0, %o1, .-4
+
+!BIN: a0: 32 c2 20 21 cwbne %o0, 1, 0xa4
+!BIN: a4: 12 c2 20 21 cwbe %o0, 1, 0xa8
+!BIN: a8: 34 c2 20 21 cwbg %o0, 1, 0xac
+!BIN: ac: 14 c2 20 21 cwble %o0, 1, 0xb0
+!BIN: b0: 36 c2 20 21 cwbge %o0, 1, 0xb4
+!BIN: b4: 16 c2 20 21 cwbl %o0, 1, 0xb8
+!BIN: b8: 38 c2 20 21 cwbgu %o0, 1, 0xbc
+!BIN: bc: 18 c2 20 21 cwbleu %o0, 1, 0xc0
+!BIN: c0: 3a c2 20 21 cwbcc %o0, 1, 0xc4
+!BIN: c4: 1a c2 20 21 cwbcs %o0, 1, 0xc8
+!BIN: c8: 3c c2 20 21 cwbpos %o0, 1, 0xcc
+!BIN: cc: 1c c2 20 21 cwbneg %o0, 1, 0xd0
+!BIN: d0: 3e c2 20 21 cwbvc %o0, 1, 0xd4
+!BIN: d4: 1e c2 20 21 cwbvs %o0, 1, 0xd8
+cwbne %o0, 1, .+4
+cwbe %o0, 1, .+4
+cwbg %o0, 1, .+4
+cwble %o0, 1, .+4
+cwbge %o0, 1, .+4
+cwbl %o0, 1, .+4
+cwbgu %o0, 1, .+4
+cwbleu %o0, 1, .+4
+cwbcc %o0, 1, .+4
+cwbcs %o0, 1, .+4
+cwbpos %o0, 1, .+4
+cwbneg %o0, 1, .+4
+cwbvc %o0, 1, .+4
+cwbvs %o0, 1, .+4
+
+!BIN: d8: 32 da 3f e1 cwbne %o0, 1, 0xd4
+!BIN: dc: 12 da 3f e1 cwbe %o0, 1, 0xd8
+!BIN: e0: 34 da 3f e1 cwbg %o0, 1, 0xdc
+!BIN: e4: 14 da 3f e1 cwble %o0, 1, 0xe0
+!BIN: e8: 36 da 3f e1 cwbge %o0, 1, 0xe4
+!BIN: ec: 16 da 3f e1 cwbl %o0, 1, 0xe8
+!BIN: f0: 38 da 3f e1 cwbgu %o0, 1, 0xec
+!BIN: f4: 18 da 3f e1 cwbleu %o0, 1, 0xf0
+!BIN: f8: 3a da 3f e1 cwbcc %o0, 1, 0xf4
+!BIN: fc: 1a da 3f e1 cwbcs %o0, 1, 0xf8
+!BIN: 100: 3c da 3f e1 cwbpos %o0, 1, 0xfc
+!BIN: 104: 1c da 3f e1 cwbneg %o0, 1, 0x100
+!BIN: 108: 3e da 3f e1 cwbvc %o0, 1, 0x104
+!BIN: 10c: 1e da 3f e1 cwbvs %o0, 1, 0x108
+cwbne %o0, 1, .-4
+cwbe %o0, 1, .-4
+cwbg %o0, 1, .-4
+cwble %o0, 1, .-4
+cwbge %o0, 1, .-4
+cwbl %o0, 1, .-4
+cwbgu %o0, 1, .-4
+cwbleu %o0, 1, .-4
+cwbcc %o0, 1, .-4
+cwbcs %o0, 1, .-4
+cwbpos %o0, 1, .-4
+cwbneg %o0, 1, .-4
+cwbvc %o0, 1, .-4
+cwbvs %o0, 1, .-4
+
+!BIN: 110: 32 e2 00 29 cxbne %o0, %o1, 0x114
+!BIN: 114: 12 e2 00 29 cxbe %o0, %o1, 0x118
+!BIN: 118: 34 e2 00 29 cxbg %o0, %o1, 0x11c
+!BIN: 11c: 14 e2 00 29 cxble %o0, %o1, 0x120
+!BIN: 120: 36 e2 00 29 cxbge %o0, %o1, 0x124
+!BIN: 124: 16 e2 00 29 cxbl %o0, %o1, 0x128
+!BIN: 128: 38 e2 00 29 cxbgu %o0, %o1, 0x12c
+!BIN: 12c: 18 e2 00 29 cxbleu %o0, %o1, 0x130
+!BIN: 130: 3a e2 00 29 cxbcc %o0, %o1, 0x134
+!BIN: 134: 1a e2 00 29 cxbcs %o0, %o1, 0x138
+!BIN: 138: 3c e2 00 29 cxbpos %o0, %o1, 0x13c
+!BIN: 13c: 1c e2 00 29 cxbneg %o0, %o1, 0x140
+!BIN: 140: 3e e2 00 29 cxbvc %o0, %o1, 0x144
+!BIN: 144: 1e e2 00 29 cxbvs %o0, %o1, 0x148
+cxbne %o0, %o1, .+4
+cxbe %o0, %o1, .+4
+cxbg %o0, %o1, .+4
+cxble %o0, %o1, .+4
+cxbge %o0, %o1, .+4
+cxbl %o0, %o1, .+4
+cxbgu %o0, %o1, .+4
+cxbleu %o0, %o1, .+4
+cxbcc %o0, %o1, .+4
+cxbcs %o0, %o1, .+4
+cxbpos %o0, %o1, .+4
+cxbneg %o0, %o1, .+4
+cxbvc %o0, %o1, .+4
+cxbvs %o0, %o1, .+4
+
+!BIN: 148: 32 fa 1f e9 cxbne %o0, %o1, 0x144
+!BIN: 14c: 12 fa 1f e9 cxbe %o0, %o1, 0x148
+!BIN: 150: 34 fa 1f e9 cxbg %o0, %o1, 0x14c
+!BIN: 154: 14 fa 1f e9 cxble %o0, %o1, 0x150
+!BIN: 158: 36 fa 1f e9 cxbge %o0, %o1, 0x154
+!BIN: 15c: 16 fa 1f e9 cxbl %o0, %o1, 0x158
+!BIN: 160: 38 fa 1f e9 cxbgu %o0, %o1, 0x15c
+!BIN: 164: 18 fa 1f e9 cxbleu %o0, %o1, 0x160
+!BIN: 168: 3a fa 1f e9 cxbcc %o0, %o1, 0x164
+!BIN: 16c: 1a fa 1f e9 cxbcs %o0, %o1, 0x168
+!BIN: 170: 3c fa 1f e9 cxbpos %o0, %o1, 0x16c
+!BIN: 174: 1c fa 1f e9 cxbneg %o0, %o1, 0x170
+!BIN: 178: 3e fa 1f e9 cxbvc %o0, %o1, 0x174
+!BIN: 17c: 1e fa 1f e9 cxbvs %o0, %o1, 0x178
+cxbne %o0, %o1, .-4
+cxbe %o0, %o1, .-4
+cxbg %o0, %o1, .-4
+cxble %o0, %o1, .-4
+cxbge %o0, %o1, .-4
+cxbl %o0, %o1, .-4
+cxbgu %o0, %o1, .-4
+cxbleu %o0, %o1, .-4
+cxbcc %o0, %o1, .-4
+cxbcs %o0, %o1, .-4
+cxbpos %o0, %o1, .-4
+cxbneg %o0, %o1, .-4
+cxbvc %o0, %o1, .-4
+cxbvs %o0, %o1, .-4
+
+!BIN: 180: 32 e2 20 21 cxbne %o0, 1, 0x184
+!BIN: 184: 12 e2 20 21 cxbe %o0, 1, 0x188
+!BIN: 188: 34 e2 20 21 cxbg %o0, 1, 0x18c
+!BIN: 18c: 14 e2 20 21 cxble %o0, 1, 0x190
+!BIN: 190: 36 e2 20 21 cxbge %o0, 1, 0x194
+!BIN: 194: 16 e2 20 21 cxbl %o0, 1, 0x198
+!BIN: 198: 38 e2 20 21 cxbgu %o0, 1, 0x19c
+!BIN: 19c: 18 e2 20 21 cxbleu %o0, 1, 0x1a0
+!BIN: 1a0: 3a e2 20 21 cxbcc %o0, 1, 0x1a4
+!BIN: 1a4: 1a e2 20 21 cxbcs %o0, 1, 0x1a8
+!BIN: 1a8: 3c e2 20 21 cxbpos %o0, 1, 0x1ac
+!BIN: 1ac: 1c e2 20 21 cxbneg %o0, 1, 0x1b0
+!BIN: 1b0: 3e e2 20 21 cxbvc %o0, 1, 0x1b4
+!BIN: 1b4: 1e e2 20 21 cxbvs %o0, 1, 0x1b8
+cxbne %o0, 1, .+4
+cxbe %o0, 1, .+4
+cxbg %o0, 1, .+4
+cxble %o0, 1, .+4
+cxbge %o0, 1, .+4
+cxbl %o0, 1, .+4
+cxbgu %o0, 1, .+4
+cxbleu %o0, 1, .+4
+cxbcc %o0, 1, .+4
+cxbcs %o0, 1, .+4
+cxbpos %o0, 1, .+4
+cxbneg %o0, 1, .+4
+cxbvc %o0, 1, .+4
+cxbvs %o0, 1, .+4
+
+!BIN: 1b8: 32 fa 3f e1 cxbne %o0, 1, 0x1b4
+!BIN: 1bc: 12 fa 3f e1 cxbe %o0, 1, 0x1b8
+!BIN: 1c0: 34 fa 3f e1 cxbg %o0, 1, 0x1bc
+!BIN: 1c4: 14 fa 3f e1 cxble %o0, 1, 0x1c0
+!BIN: 1c8: 36 fa 3f e1 cxbge %o0, 1, 0x1c4
+!BIN: 1cc: 16 fa 3f e1 cxbl %o0, 1, 0x1c8
+!BIN: 1d0: 38 fa 3f e1 cxbgu %o0, 1, 0x1cc
+!BIN: 1d4: 18 fa 3f e1 cxbleu %o0, 1, 0x1d0
+!BIN: 1d8: 3a fa 3f e1 cxbcc %o0, 1, 0x1d4
+!BIN: 1dc: 1a fa 3f e1 cxbcs %o0, 1, 0x1d8
+!BIN: 1e0: 3c fa 3f e1 cxbpos %o0, 1, 0x1dc
+!BIN: 1e4: 1c fa 3f e1 cxbneg %o0, 1, 0x1e0
+!BIN: 1e8: 3e fa 3f e1 cxbvc %o0, 1, 0x1e4
+!BIN: 1ec: 1e fa 3f e1 cxbvs %o0, 1, 0x1e8
+cxbne %o0, 1, .-4
+cxbe %o0, 1, .-4
+cxbg %o0, 1, .-4
+cxble %o0, 1, .-4
+cxbge %o0, 1, .-4
+cxbl %o0, 1, .-4
+cxbgu %o0, 1, .-4
+cxbleu %o0, 1, .-4
+cxbcc %o0, 1, .-4
+cxbcs %o0, 1, .-4
+cxbpos %o0, 1, .-4
+cxbneg %o0, 1, .-4
+cxbvc %o0, 1, .-4
+cxbvs %o0, 1, .-4
More information about the llvm-commits
mailing list