[llvm] [NFC][PowerpC] Add testcases for locking down the xxeval instruction support for ternary operators (PR #141601)
Tony Varghese via llvm-commits
llvm-commits at lists.llvm.org
Thu May 29 08:04:53 PDT 2025
https://github.com/tonykuttai updated https://github.com/llvm/llvm-project/pull/141601
>From 46eeffca9c0a51f724eb6f859a8ff9778686619e Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Tue, 27 May 2025 13:36:08 +0000
Subject: [PATCH 01/10] [NFC] Add testcases for locking down the xxeval
instruction support for ternary operators
---
.../CodeGen/PowerPC/xxeval-vselect-x-and.ll | 188 ++++++++++++++++++
.../CodeGen/PowerPC/xxeval-vselect-x-b.ll | 169 ++++++++++++++++
.../CodeGen/PowerPC/xxeval-vselect-x-c.ll | 138 +++++++++++++
.../CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 177 +++++++++++++++++
4 files changed, 672 insertions(+)
create mode 100644 llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
create mode 100644 llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
create mode 100644 llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
create mode 100644 llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
new file mode 100644
index 0000000000000..05fb6534bebcd
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -0,0 +1,188 @@
+; Test file to verify the emission of Vector selection instructions when ternary operators are used.
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %xor, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, xor(B, C), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64
+; CHECK: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %xor, <2 x i64> %and
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %and
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %and
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_not_C_and_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_not_B_and_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
+ ret <2 x i64> %res
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
new file mode 100644
index 0000000000000..3966c69636986
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -0,0 +1,169 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, and(B, C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_and_BC_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, and(B, C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_and_BC_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %B
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_nor_BC_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_nor_BC_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %B
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_eqv_BC_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %B
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, not(C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_not_C_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
+ %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, not(C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_not_C_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
+ %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %B
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nand(B, C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_nand_BC_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
+ %res = select <4 x i1> %A, <4 x i32> %nand, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nand(B, C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_nand_BC_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
+ %res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %B
+ ret <2 x i64> %res
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
new file mode 100644
index 0000000000000..76ff1b2f2f683
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -0,0 +1,138 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, and(B, C), C) for <4 x i32>
+; CHECK-LABEL: ternary_A_and_BC_C_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %C
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, and(B, C), C) for <2 x i64>
+; CHECK-LABEL: ternary_A_and_BC_C_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %C
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), C) for <4 x i32>
+; CHECK-LABEL: ternary_A_nor_BC_C_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %C
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), C) for <2 x i64>
+; CHECK-LABEL: ternary_A_nor_BC_C_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %C
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
+; CHECK-LABEL: ternary_A_eqv_BC_C_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %C
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, eqv(B, C), C) for <2 x i64>
+; CHECK-LABEL: ternary_A_eqv_BC_C_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %C
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nand(B, C), C) for <4 x i32>
+; CHECK-LABEL: ternary_A_nand_BC_C_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
+ %res = select <4 x i1> %A, <4 x i32> %nand, <4 x i32> %C
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nand(B, C), C) for <2 x i64>
+; CHECK-LABEL: ternary_A_nand_BC_C_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
+ %res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %C
+ ret <2 x i64> %res
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
new file mode 100644
index 0000000000000..0a919bc982c85
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -0,0 +1,177 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, and(B, C), xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, and(B, C), xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %xor
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_B_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %B, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, B, xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_B_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %B, <2 x i64> %xor
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_C_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %C, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, C, xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_C_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %C, <2 x i64> %xor
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, or(B, C), xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %or, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, or(B, C), xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %or, <2 x i64> %xor
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; vector nor operation
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; vector nor operation
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %xor
+ ret <2 x i64> %res
+}
>From f4010619d6a75ebc62b49d1081bfb007c6636610 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 04:58:44 +0000
Subject: [PATCH 02/10] Removed the xxspltiw instructions from the check
---
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll | 15 +++++----------
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll | 15 +++++----------
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll | 12 ++++--------
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 15 +++++----------
4 files changed, 19 insertions(+), 38 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
index 05fb6534bebcd..e65e41adb0df7 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -11,8 +11,7 @@
; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -45,8 +44,7 @@ entry:
; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -82,8 +80,7 @@ entry:
; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -119,8 +116,7 @@ entry:
; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK: xxlnor vs0, v4, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -154,8 +150,7 @@ entry:
; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK: xxlnor vs0, v3, v3
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index 3966c69636986..8ae82d7c6a275 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -9,8 +9,7 @@
; Function to test ternary(A, and(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
@@ -40,8 +39,7 @@ entry:
; Function to test ternary(A, nor(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
@@ -73,8 +71,7 @@ entry:
; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
@@ -106,8 +103,7 @@ entry:
; Function to test ternary(A, not(C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_not_C_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK: xxlnor vs0, v4, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
@@ -137,8 +133,7 @@ entry:
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_nand_BC_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK: xxlnand vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index 76ff1b2f2f683..a53c0b845732b 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -9,8 +9,7 @@
; Function to test ternary(A, and(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_C_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v4, vs0, v2
@@ -40,8 +39,7 @@ entry:
; Function to test ternary(A, nor(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_C_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v4, vs0, v2
@@ -73,8 +71,7 @@ entry:
; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_C_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v4, vs0, v2
@@ -106,8 +103,7 @@ entry:
; Function to test ternary(A, nand(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_nand_BC_C_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK: xxlnand vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v4, vs0, v2
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index 0a919bc982c85..25b6fd6e4c540 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -9,8 +9,7 @@
; Function to test ternary(A, and(B, C), xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -44,8 +43,7 @@ entry:
; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_B_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, vs0, v3, v2
@@ -75,8 +73,7 @@ entry:
; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_C_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, vs0, v4, v2
@@ -106,8 +103,7 @@ entry:
; Function to test ternary(A, or(B, C), xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK: xxlor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -141,8 +137,7 @@ entry:
; Function to test ternary(A, nor(B, C), xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
>From 2b8924ad169b9eefce9ff20c2dbf5a7ff6543d45 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 06:09:34 +0000
Subject: [PATCH 03/10] Add test summary
---
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll | 2 ++
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll | 2 ++
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 2 ++
3 files changed, 6 insertions(+)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index 8ae82d7c6a275..a04c2500ea91a 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -1,3 +1,5 @@
+; Test file to verify the emission of Vector selection instructions when ternary operators are used.
+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index a53c0b845732b..5b5b5eaeb50cf 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -1,3 +1,5 @@
+; Test file to verify the emission of Vector selection instructions when ternary operators are used.
+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index 25b6fd6e4c540..dcdf463b924e1 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -1,3 +1,5 @@
+; Test file to verify the emission of Vector selection instructions when ternary operators are used.
+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
>From 5db66cfbf282042135ffc06c3da93865c8783526 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 09:02:10 +0000
Subject: [PATCH 04/10] Modified test files to capture only the essential
instructions
---
.../CodeGen/PowerPC/xxeval-vselect-x-and.ll | 57 +++++-------------
.../CodeGen/PowerPC/xxeval-vselect-x-b.ll | 60 +++++--------------
.../CodeGen/PowerPC/xxeval-vselect-x-c.ll | 48 ++++-----------
.../CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 60 +++++--------------
4 files changed, 56 insertions(+), 169 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
index e65e41adb0df7..7187d3bf30f0e 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -13,9 +13,7 @@
; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -29,10 +27,7 @@ entry:
; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64
; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -46,9 +41,7 @@ entry:
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -61,13 +54,9 @@ entry:
; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -82,9 +71,7 @@ entry:
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -97,13 +84,9 @@ entry:
; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -118,9 +101,7 @@ entry:
; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
; CHECK: xxlnor vs0, v4, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -132,13 +113,9 @@ entry:
; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_not_C_and_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK: xxlnor vs0, v4, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -152,9 +129,7 @@ entry:
; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
; CHECK: xxlnor vs0, v3, v3
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -166,13 +141,9 @@ entry:
; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_not_B_and_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK: xxlnor vs0, v3, v3
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index a04c2500ea91a..7f9741d7d37f7 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -12,9 +12,7 @@
; Function to test ternary(A, and(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_B_4x32
; CHECK: xxland vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -25,12 +23,8 @@ entry:
; Function to test ternary(A, and(B, C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_and_BC_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxland vs0, v3, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -42,9 +36,7 @@ entry:
; Function to test ternary(A, nor(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_B_4x32
; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -56,12 +48,8 @@ entry:
; Function to test ternary(A, nor(B, C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxlnor vs0, v3, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -74,9 +62,7 @@ entry:
; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
; CHECK: xxleqv vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -88,12 +74,8 @@ entry:
; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_eqv_BC_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxleqv vs0, v3, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -106,9 +88,7 @@ entry:
; Function to test ternary(A, not(C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_not_C_B_4x32
; CHECK: xxlnor vs0, v4, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -119,12 +99,8 @@ entry:
; Function to test ternary(A, not(C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_not_C_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v4, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxlnor vs0, v4, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -136,9 +112,7 @@ entry:
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_nand_BC_B_4x32
; CHECK: xxlnand vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -150,12 +124,8 @@ entry:
; Function to test ternary(A, nand(B, C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_nand_BC_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnand vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxlnand vs0, v3, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index 5b5b5eaeb50cf..ba614941cfea4 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -12,9 +12,7 @@
; Function to test ternary(A, and(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_C_4x32
; CHECK: xxland vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -25,12 +23,8 @@ entry:
; Function to test ternary(A, and(B, C), C) for <2 x i64>
; CHECK-LABEL: ternary_A_and_BC_C_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxland vs0, v3, v4
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -42,9 +36,7 @@ entry:
; Function to test ternary(A, nor(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_C_4x32
; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -56,12 +48,8 @@ entry:
; Function to test ternary(A, nor(B, C), C) for <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_C_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxlnor vs0, v3, v4
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -74,9 +62,7 @@ entry:
; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_C_4x32
; CHECK: xxleqv vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -88,12 +74,8 @@ entry:
; Function to test ternary(A, eqv(B, C), C) for <2 x i64>
; CHECK-LABEL: ternary_A_eqv_BC_C_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxleqv vs0, v3, v4
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -106,9 +88,7 @@ entry:
; Function to test ternary(A, nand(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_nand_BC_C_4x32
; CHECK: xxlnand vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -120,12 +100,8 @@ entry:
; Function to test ternary(A, nand(B, C), C) for <2 x i64>
; CHECK-LABEL: ternary_A_nand_BC_C_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnand vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxlnand vs0, v3, v4
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index dcdf463b924e1..dfce8ef56ba01 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -13,9 +13,7 @@
; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32
; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -27,13 +25,9 @@ entry:
; Function to test ternary(A, and(B, C), xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -46,9 +40,7 @@ entry:
; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_B_xor_BC_4x32
; CHECK: xxlxor vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK: xxsel v2, vs0, v3, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -59,12 +51,8 @@ entry:
; Function to test ternary(A, B, xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_B_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK: xxlxor vs0, v3, v4
+; CHECK: xxsel v2, vs0, v3, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -76,9 +64,7 @@ entry:
; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_C_xor_BC_4x32
; CHECK: xxlxor vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK: xxsel v2, vs0, v4, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -89,12 +75,8 @@ entry:
; Function to test ternary(A, C, xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_C_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK: xxlxor vs0, v3, v4
+; CHECK: xxsel v2, vs0, v4, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -107,9 +89,7 @@ entry:
; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32
; CHECK: xxlor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -121,13 +101,9 @@ entry:
; Function to test ternary(A, or(B, C), xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK: xxlor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -141,9 +117,7 @@ entry:
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32
; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -156,13 +130,9 @@ entry:
; Function to test ternary(A, nor(B, C), xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
>From 0c1b7d0b7362f4eda1ee021c927deee97acd359a Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 17:25:12 +0000
Subject: [PATCH 05/10] Updated tests using update_llc_test_checks.py
---
.../CodeGen/PowerPC/xxeval-vselect-x-and.ll | 148 ++++++++++++------
.../CodeGen/PowerPC/xxeval-vselect-x-b.ll | 128 ++++++++++-----
.../CodeGen/PowerPC/xxeval-vselect-x-c.ll | 103 ++++++++----
.../CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 138 ++++++++++------
4 files changed, 346 insertions(+), 171 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
index 7187d3bf30f0e..c07db2c584ed2 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
@@ -10,12 +11,16 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
-; CHECK: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%and = and <4 x i32> %B, %C
@@ -24,12 +29,17 @@ entry:
}
; Function to test ternary(A, xor(B, C), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64
-; CHECK: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%and = and <2 x i64> %B, %C
@@ -38,12 +48,16 @@ entry:
}
; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
-; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
@@ -53,12 +67,17 @@ entry:
}
; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64
-; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
@@ -68,12 +87,16 @@ entry:
}
; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
-; CHECK: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
@@ -83,12 +106,17 @@ entry:
}
; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64
-; CHECK: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
@@ -98,12 +126,16 @@ entry:
}
; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
-; CHECK: xxlnor vs0, v4, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_C_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
%and = and <4 x i32> %B, %C
@@ -112,12 +144,17 @@ entry:
}
; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_not_C_and_BC_2x64
-; CHECK: xxlnor vs0, v4, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_C_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
%and = and <2 x i64> %B, %C
@@ -126,12 +163,16 @@ entry:
}
; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
-; CHECK: xxlnor vs0, v3, v3
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_B_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
%and = and <4 x i32> %B, %C
@@ -140,15 +181,20 @@ entry:
}
; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_not_B_and_BC_2x64
-; CHECK: xxlnor vs0, v3, v3
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_B_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation
%and = and <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
ret <2 x i64> %res
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index 7f9741d7d37f7..dc22b5786b695 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
@@ -10,11 +11,15 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_and_BC_B_4x32
-; CHECK: xxland vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %B
@@ -22,11 +27,16 @@ entry:
}
; Function to test ternary(A, and(B, C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_and_BC_B_2x64
-; CHECK: xxland vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %B
@@ -34,11 +44,15 @@ entry:
}
; Function to test ternary(A, nor(B, C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_nor_BC_B_4x32
-; CHECK: xxlnor vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
@@ -47,11 +61,16 @@ entry:
}
; Function to test ternary(A, nor(B, C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_nor_BC_B_2x64
-; CHECK: xxlnor vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
@@ -60,11 +79,15 @@ entry:
}
; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
-; CHECK: xxleqv vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
@@ -73,11 +96,16 @@ entry:
}
; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_eqv_BC_B_2x64
-; CHECK: xxleqv vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
@@ -86,11 +114,15 @@ entry:
}
; Function to test ternary(A, not(C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_not_C_B_4x32
-; CHECK: xxlnor vs0, v4, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_C_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %B
@@ -98,11 +130,16 @@ entry:
}
; Function to test ternary(A, not(C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_not_C_B_2x64
-; CHECK: xxlnor vs0, v4, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_C_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %B
@@ -110,11 +147,15 @@ entry:
}
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_nand_BC_B_4x32
-; CHECK: xxlnand vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nand_BC_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
@@ -123,14 +164,19 @@ entry:
}
; Function to test ternary(A, nand(B, C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_nand_BC_B_2x64
-; CHECK: xxlnand vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nand_BC_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
%res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %B
ret <2 x i64> %res
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index ba614941cfea4..59f046ced9a8e 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
@@ -10,11 +11,15 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), C) for <4 x i32>
-; CHECK-LABEL: ternary_A_and_BC_C_4x32
-; CHECK: xxland vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_C_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %C
@@ -22,11 +27,16 @@ entry:
}
; Function to test ternary(A, and(B, C), C) for <2 x i64>
-; CHECK-LABEL: ternary_A_and_BC_C_2x64
-; CHECK: xxland vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_C_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %C
@@ -34,11 +44,15 @@ entry:
}
; Function to test ternary(A, nor(B, C), C) for <4 x i32>
-; CHECK-LABEL: ternary_A_nor_BC_C_4x32
-; CHECK: xxlnor vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_C_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
@@ -47,11 +61,16 @@ entry:
}
; Function to test ternary(A, nor(B, C), C) for <2 x i64>
-; CHECK-LABEL: ternary_A_nor_BC_C_2x64
-; CHECK: xxlnor vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_C_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
@@ -60,11 +79,15 @@ entry:
}
; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
-; CHECK-LABEL: ternary_A_eqv_BC_C_4x32
-; CHECK: xxleqv vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_C_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
@@ -73,11 +96,16 @@ entry:
}
; Function to test ternary(A, eqv(B, C), C) for <2 x i64>
-; CHECK-LABEL: ternary_A_eqv_BC_C_2x64
-; CHECK: xxleqv vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_C_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
@@ -86,11 +114,15 @@ entry:
}
; Function to test ternary(A, nand(B, C), C) for <4 x i32>
-; CHECK-LABEL: ternary_A_nand_BC_C_4x32
-; CHECK: xxlnand vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nand_BC_C_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
@@ -99,14 +131,19 @@ entry:
}
; Function to test ternary(A, nand(B, C), C) for <2 x i64>
-; CHECK-LABEL: ternary_A_nand_BC_C_2x64
-; CHECK: xxlnand vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nand_BC_C_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
%res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %C
ret <2 x i64> %res
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index dfce8ef56ba01..88f8bb29dc337 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
@@ -10,12 +11,16 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32
-; CHECK: xxland vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%xor = xor <4 x i32> %B, %C
@@ -24,12 +29,17 @@ entry:
}
; Function to test ternary(A, and(B, C), xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64
-; CHECK: xxland vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%xor = xor <2 x i64> %B, %C
@@ -38,11 +48,15 @@ entry:
}
; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_B_xor_BC_4x32
-; CHECK: xxlxor vs0, v3, v4
-; CHECK: xxsel v2, vs0, v3, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_B_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%res = select <4 x i1> %A, <4 x i32> %B, <4 x i32> %xor
@@ -50,11 +64,16 @@ entry:
}
; Function to test ternary(A, B, xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_B_xor_BC_2x64
-; CHECK: xxlxor vs0, v3, v4
-; CHECK: xxsel v2, vs0, v3, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_B_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %B, <2 x i64> %xor
@@ -62,11 +81,15 @@ entry:
}
; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_C_xor_BC_4x32
-; CHECK: xxlxor vs0, v3, v4
-; CHECK: xxsel v2, vs0, v4, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_C_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%res = select <4 x i1> %A, <4 x i32> %C, <4 x i32> %xor
@@ -74,11 +97,16 @@ entry:
}
; Function to test ternary(A, C, xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_C_xor_BC_2x64
-; CHECK: xxlxor vs0, v3, v4
-; CHECK: xxsel v2, vs0, v4, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_C_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %C, <2 x i64> %xor
@@ -86,12 +114,16 @@ entry:
}
; Function to test ternary(A, or(B, C), xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32
-; CHECK: xxlor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%xor = xor <4 x i32> %B, %C
@@ -100,12 +132,17 @@ entry:
}
; Function to test ternary(A, or(B, C), xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64
-; CHECK: xxlor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%xor = xor <2 x i64> %B, %C
@@ -114,12 +151,16 @@ entry:
}
; Function to test ternary(A, nor(B, C), xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32
-; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; vector nor operation
@@ -129,12 +170,17 @@ entry:
}
; Function to test ternary(A, nor(B, C), xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64
-; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; vector nor operation
>From 6185f5a0201ff76a0569061cfcd4700aae1eb827 Mon Sep 17 00:00:00 2001
From: Alan Li <me at alanli.org>
Date: Tue, 8 Apr 2025 07:46:55 -0700
Subject: [PATCH 06/10] [MLIR][Fix] Fix missing dep in AMDGPUDialect. (#134862)
Issue introduced in https://github.com/llvm/llvm-project/pull/133498
>From 9a125671bb5340be2c10efa87a1148ebecdd831f Mon Sep 17 00:00:00 2001
From: Amr Hesham <amr96 at programmer.net>
Date: Mon, 21 Apr 2025 20:07:01 +0200
Subject: [PATCH 07/10] [CIR][NFC] Fix an unused variable warning (#136431)
This fixes a warning where a variable assigned in 'if' statement wasn't
referenced again.
>From 5ea7ac57dc15a88cddd463012ff101cc04efd40a Mon Sep 17 00:00:00 2001
From: Aaron Ballman <aaron at aaronballman.com>
Date: Tue, 29 Apr 2025 07:57:03 -0400
Subject: [PATCH 08/10] Fix crash with -ast-dump=json (#137324)
When given an invalid Objective-C extension, Clang would crash when
trying to emit the mangled name of the method to the JSON dump output.
Fixes #137320
>From 71d4680eb2f993ad9ac7f02b17dc583830b17b7c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?=
=?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?=
=?UTF-8?q?=E3=83=B3=29?= <clementval at gmail.com>
Date: Thu, 22 May 2025 08:24:18 -0700
Subject: [PATCH 09/10] [flang][rt] Fix the use of kNoAsyncId -> kNoAsyncObject
(#141079)
>From 685e5ada0789acc22dfda95e87ad1ba93633de00 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Thu, 29 May 2025 15:04:08 +0000
Subject: [PATCH 10/10] Rebased the branch with the latest main.Updated tests
using update_llc_test_checks.py
---
.../CodeGen/PowerPC/xxeval-vselect-x-and.ll | 30 +++++++++----------
.../CodeGen/PowerPC/xxeval-vselect-x-b.ll | 30 +++++++++----------
.../CodeGen/PowerPC/xxeval-vselect-x-c.ll | 24 +++++++--------
.../CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 30 +++++++++----------
4 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
index c07db2c584ed2..2868669c52ce6 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -11,10 +11,10 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlxor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
@@ -29,7 +29,7 @@ entry:
}
; Function to test ternary(A, xor(B, C), and(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -48,10 +48,10 @@ entry:
}
; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
@@ -67,7 +67,7 @@ entry:
}
; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -87,10 +87,10 @@ entry:
}
; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxleqv vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
@@ -106,7 +106,7 @@ entry:
}
; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -126,10 +126,10 @@ entry:
}
; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_not_C_and_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnor vs0, v4, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
@@ -144,7 +144,7 @@ entry:
}
; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_not_C_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -163,10 +163,10 @@ entry:
}
; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_not_B_and_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnor vs0, v3, v3
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
@@ -181,7 +181,7 @@ entry:
}
; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_not_B_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index dc22b5786b695..37a0edb14b78f 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -11,10 +11,10 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), B) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_and_BC_B_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxland vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -27,7 +27,7 @@ entry:
}
; Function to test ternary(A, and(B, C), B) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_and_BC_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -44,10 +44,10 @@ entry:
}
; Function to test ternary(A, nor(B, C), B) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_nor_BC_B_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -61,7 +61,7 @@ entry:
}
; Function to test ternary(A, nor(B, C), B) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_nor_BC_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -79,10 +79,10 @@ entry:
}
; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_eqv_BC_B_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxleqv vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -96,7 +96,7 @@ entry:
}
; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_eqv_BC_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -114,10 +114,10 @@ entry:
}
; Function to test ternary(A, not(C), B) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_not_C_B_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnor vs0, v4, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -130,7 +130,7 @@ entry:
}
; Function to test ternary(A, not(C), B) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_not_C_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -147,10 +147,10 @@ entry:
}
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_nand_BC_B_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnand vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -164,7 +164,7 @@ entry:
}
; Function to test ternary(A, nand(B, C), B) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_nand_BC_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index 59f046ced9a8e..411aa27a61861 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -11,10 +11,10 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), C) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_and_BC_C_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxland vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -27,7 +27,7 @@ entry:
}
; Function to test ternary(A, and(B, C), C) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_and_BC_C_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -44,10 +44,10 @@ entry:
}
; Function to test ternary(A, nor(B, C), C) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_nor_BC_C_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -61,7 +61,7 @@ entry:
}
; Function to test ternary(A, nor(B, C), C) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_nor_BC_C_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -79,10 +79,10 @@ entry:
}
; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_eqv_BC_C_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxleqv vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -96,7 +96,7 @@ entry:
}
; Function to test ternary(A, eqv(B, C), C) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_eqv_BC_C_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -114,10 +114,10 @@ entry:
}
; Function to test ternary(A, nand(B, C), C) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_nand_BC_C_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnand vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -131,7 +131,7 @@ entry:
}
; Function to test ternary(A, nand(B, C), C) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_nand_BC_C_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index 88f8bb29dc337..f8a8b6e9a0486 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -11,10 +11,10 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), xor(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxland vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
@@ -29,7 +29,7 @@ entry:
}
; Function to test ternary(A, and(B, C), xor(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -48,10 +48,10 @@ entry:
}
; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_B_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlxor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -64,7 +64,7 @@ entry:
}
; Function to test ternary(A, B, xor(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_B_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -81,10 +81,10 @@ entry:
}
; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_C_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlxor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -97,7 +97,7 @@ entry:
}
; Function to test ternary(A, C, xor(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_C_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -114,10 +114,10 @@ entry:
}
; Function to test ternary(A, or(B, C), xor(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
@@ -132,7 +132,7 @@ entry:
}
; Function to test ternary(A, or(B, C), xor(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
@@ -151,10 +151,10 @@ entry:
}
; Function to test ternary(A, nor(B, C), xor(B, C)) for <4 x i32>
-define dso_local <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+define <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv v5, v5, v5
; CHECK-NEXT: xxlnor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
@@ -170,7 +170,7 @@ entry:
}
; Function to test ternary(A, nor(B, C), xor(B, C)) for <2 x i64>
-define dso_local <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+define <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
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