[llvm] baeec97 - [RISCV] Canonicalize beq/bne with x0 as first arg to beqz/bnez (#141781)

[via llvm-commits]

Author: Alex Bradbury
Date: 2025-05-29T11:28:45+01:00
New Revision: baeec97ebd1ce7043f86f3cd294b9d967afb5f81

URL: https://github.com/llvm/llvm-project/commit/baeec97ebd1ce7043f86f3cd294b9d967afb5f81
DIFF: https://github.com/llvm/llvm-project/commit/baeec97ebd1ce7043f86f3cd294b9d967afb5f81.diff

LOG: [RISCV] Canonicalize beq/bne with x0 as first arg to beqz/bnez (#141781)

This covers similar ground as #139086. Although I think it makes sense
to land both, the practical motivation for #139086 is significantly
reduced here.

This canonicalisation makes no difference to compressibility (we have
compress patterns for the operands in either order), but it does mean
that easier to read assembly is printed, as we don't have aliases
defined for beq/bne with x0 in either position.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 02656c4b288e4..09a464324b967 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4189,6 +4189,15 @@ bool RISCVInstrInfo::simplifyInstruction(MachineInstr &MI) const {
       return true;
     }
     break;
+  case RISCV::BEQ:
+  case RISCV::BNE:
+    // b{eq,ne} zero, rs, imm => b{eq,ne} rs, zero, imm
+    if (MI.getOperand(0).getReg() == RISCV::X0) {
+      MachineOperand MO0 = MI.getOperand(0);
+      MI.removeOperand(0);
+      MI.insert(MI.operands_begin() + 1, {MO0});
+    }
+    break;
   case RISCV::BLTU:
     // bltu zero, rs, imm => bne rs, zero, imm
     if (MI.getOperand(0).getReg() == RISCV::X0) {

diff  --git a/llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir b/llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir
index 9e42783e44553..e329028ac0b84 100644
--- a/llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir
+++ b/llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir
@@ -743,6 +743,42 @@ body: |
     PseudoRET implicit $x10
 ...
 ---
+name: beq
+body: |
+  ; CHECK-LABEL: name: beq
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   renamable $x11 = COPY $x12
+  ; CHECK-NEXT:   BEQ $x12, $x0, %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   PseudoRET
+  bb.0:
+    renamable $x11 = COPY $x12
+    BEQ $x0, renamable $x11, %bb.1
+  bb.1:
+    PseudoRET
+...
+---
+name: bne
+body: |
+  ; CHECK-LABEL: name: bne
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   renamable $x11 = COPY $x12
+  ; CHECK-NEXT:   BNE $x12, $x0, %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   PseudoRET
+  bb.0:
+    renamable $x11 = COPY $x12
+    BNE $x0, renamable $x11, %bb.1
+  bb.1:
+    PseudoRET
+...
+---
 name: bltu
 body: |
   ; CHECK-LABEL: name: bltu