[llvm] [RISCV] Add BREV8 to SimplifyDemandedBitsForTargetNode. (PR #141898)

[Pengcheng Wang via llvm-commits]

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@@ -20575,8 +20575,7 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
     bool IsGORC = Op.getOpcode() == RISCVISD::ORC_B;
     // To compute zeros, we need to invert the value and invert it back after.
-    Known.Zero =
-        ~computeGREVOrGORC(~Known.Zero.getZExtValue(), 7, IsGORC);
+    Known.Zero = ~computeGREVOrGORC(~Known.Zero.getZExtValue(), 7, IsGORC);
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wangpc-pp wrote:

Why is this line re-formatted? I don't see any change?

https://github.com/llvm/llvm-project/pull/141898