[llvm] a7322d7 - [Xtensa] Implement Xtensa Region Protection Option and several other small Options. (#137135)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 29 01:04:34 PDT 2025
Author: Andrei Safronov
Date: 2025-05-29T11:04:30+03:00
New Revision: a7322d7948637aa45e9d86162601a97eb0ac2668
URL: https://github.com/llvm/llvm-project/commit/a7322d7948637aa45e9d86162601a97eb0ac2668
DIFF: https://github.com/llvm/llvm-project/commit/a7322d7948637aa45e9d86162601a97eb0ac2668.diff
LOG: [Xtensa] Implement Xtensa Region Protection Option and several other small Options. (#137135)
Implement support of the Xtensa Region Protection, Extended L32R, Data
Cache, Relocatable Vector and MISC Special Registers Options.
Added:
llvm/test/MC/Disassembler/Xtensa/clamps.txt
llvm/test/MC/Disassembler/Xtensa/dcache.txt
llvm/test/MC/Disassembler/Xtensa/div.txt
llvm/test/MC/Disassembler/Xtensa/extendedl32r.txt
llvm/test/MC/Disassembler/Xtensa/loop.txt
llvm/test/MC/Disassembler/Xtensa/mac16.txt
llvm/test/MC/Disassembler/Xtensa/minmax.txt
llvm/test/MC/Disassembler/Xtensa/miscsr.txt
llvm/test/MC/Disassembler/Xtensa/mul.txt
llvm/test/MC/Disassembler/Xtensa/mul16.txt
llvm/test/MC/Disassembler/Xtensa/mul32high.txt
llvm/test/MC/Disassembler/Xtensa/nsa.txt
llvm/test/MC/Disassembler/Xtensa/region_protect.txt
llvm/test/MC/Disassembler/Xtensa/rvector.txt
llvm/test/MC/Disassembler/Xtensa/sext.txt
llvm/test/MC/Xtensa/clamps-invalid.s
llvm/test/MC/Xtensa/clamps.s
llvm/test/MC/Xtensa/dcache.s
llvm/test/MC/Xtensa/extendedl32r.s
llvm/test/MC/Xtensa/miscsr.s
llvm/test/MC/Xtensa/region_protect.s
llvm/test/MC/Xtensa/rvector.s
Modified:
llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
llvm/lib/Target/Xtensa/XtensaFeatures.td
llvm/lib/Target/Xtensa/XtensaInstrInfo.td
llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
llvm/lib/Target/Xtensa/XtensaSubtarget.h
llvm/test/MC/Disassembler/Xtensa/code_density.txt
llvm/test/MC/Xtensa/xtensa-mac16.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index 6b355e6363b22..dbd34964db074 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -105,18 +105,27 @@ static const MCPhysReg MR23DecoderTable[] = {Xtensa::M2, Xtensa::M3};
static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo != 2 && RegNo != 3)
+ if (RegNo != 0 && RegNo != 1)
return MCDisassembler::Fail;
- MCPhysReg Reg = MR23DecoderTable[RegNo - 2];
+ MCPhysReg Reg = MR23DecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
-const MCPhysReg SRDecoderTable[] = {
- Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
- Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
- Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
+struct DecodeRegister {
+ MCPhysReg Reg;
+ uint32_t RegNo;
+};
+
+const DecodeRegister SRDecoderTable[] = {
+ {Xtensa::LBEG, 0}, {Xtensa::LEND, 1}, {Xtensa::LCOUNT, 2},
+ {Xtensa::SAR, 3}, {Xtensa::BREG, 4}, {Xtensa::SAR, 3},
+ {Xtensa::LITBASE, 5}, {Xtensa::ACCLO, 16}, {Xtensa::ACCHI, 17},
+ {Xtensa::M0, 32}, {Xtensa::M1, 33}, {Xtensa::M2, 34},
+ {Xtensa::M3, 35}, {Xtensa::WINDOWBASE, 72}, {Xtensa::WINDOWSTART, 73},
+ {Xtensa::MEMCTL, 97}, {Xtensa::VECBASE, 231}, {Xtensa::MISC0, 244},
+ {Xtensa::MISC1, 245}, {Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}};
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
@@ -124,9 +133,9 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
if (RegNo > 255)
return MCDisassembler::Fail;
- for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) {
- if (SRDecoderTable[i + 1] == RegNo) {
- MCPhysReg Reg = SRDecoderTable[i];
+ for (unsigned i = 0; i < std::size(SRDecoderTable); i++) {
+ if (SRDecoderTable[i].RegNo == RegNo) {
+ MCPhysReg Reg = SRDecoderTable[i].Reg;
if (!Xtensa::checkRegister(Reg,
Decoder->getSubtargetInfo().getFeatureBits()))
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
index 0daf333427263..63fed46ac411f 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
@@ -83,6 +83,24 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits) {
case Xtensa::LEND:
case Xtensa::LCOUNT:
return FeatureBits[Xtensa::FeatureLoop];
+ case Xtensa::LITBASE:
+ return FeatureBits[Xtensa::FeatureExtendedL32R];
+ case Xtensa::MEMCTL:
+ return FeatureBits[Xtensa::FeatureDataCache];
+ case Xtensa::ACCLO:
+ case Xtensa::ACCHI:
+ case Xtensa::M0:
+ case Xtensa::M1:
+ case Xtensa::M2:
+ case Xtensa::M3:
+ return FeatureBits[Xtensa::FeatureMAC16];
+ case Xtensa::MISC0:
+ case Xtensa::MISC1:
+ case Xtensa::MISC2:
+ case Xtensa::MISC3:
+ return FeatureBits[Xtensa::FeatureMiscSR];
+ case Xtensa::VECBASE:
+ return FeatureBits[Xtensa::FeatureRelocatableVector];
case Xtensa::WINDOWBASE:
case Xtensa::WINDOWSTART:
return FeatureBits[Xtensa::FeatureWindowed];
diff --git a/llvm/lib/Target/Xtensa/XtensaFeatures.td b/llvm/lib/Target/Xtensa/XtensaFeatures.td
index 2a47214946401..55977277daf8e 100644
--- a/llvm/lib/Target/Xtensa/XtensaFeatures.td
+++ b/llvm/lib/Target/Xtensa/XtensaFeatures.td
@@ -67,3 +67,28 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
"Enable Xtensa Div32 option">;
def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
AssemblerPredicate<(all_of FeatureDiv32)>;
+
+def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true",
+ "Enable Xtensa Region Protection option">;
+def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">,
+ AssemblerPredicate<(all_of FeatureRegionProtection)>;
+
+def FeatureRelocatableVector : SubtargetFeature<"rvector", "HasRelocatableVector", "true",
+ "Enable Xtensa Relocatable Vector option">;
+def HasRelocatableVector : Predicate<"Subtarget->hasRelocatableVector()">,
+ AssemblerPredicate<(all_of FeatureRelocatableVector)>;
+
+def FeatureMiscSR : SubtargetFeature<"miscsr", "HasMiscSR", "true",
+ "Enable Xtensa Miscellaneous SR option">;
+def HasMiscSR : Predicate<"Subtarget->hasMiscSR()">,
+ AssemblerPredicate<(all_of FeatureMiscSR)>;
+
+def FeatureExtendedL32R : SubtargetFeature<"extendedl32r", "HasExtendedL32R", "true",
+ "Enable Xtensa Extended L32R option">;
+def HasExtendedL32R : Predicate<"Subtarget->hasExtendedL32R()">,
+ AssemblerPredicate<(all_of FeatureExtendedL32R)>;
+
+def FeatureDataCache : SubtargetFeature<"dcache", "HasDataCache", "true",
+ "Enable Xtensa Data Cache option">;
+def HasDataCache : Predicate<"Subtarget->hasDataCache()">,
+ AssemblerPredicate<(all_of FeatureDataCache)>;
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index 0bd3ba81340ff..9a9424f916996 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -986,6 +986,64 @@ let Predicates = [HasDiv32] in {
def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;
}
+//===----------------------------------------------------------------------===//
+// Region Protection feature instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasRegionProtection] in {
+ def IDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
+ "idtlb\t$s", []> {
+ let r = 0xC;
+ let t = 0x0;
+ }
+
+ def IITLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
+ "iitlb\t$s", []> {
+ let r = 0x4;
+ let t = 0x0;
+ }
+
+ def PDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "pdtlb\t$t, $s", []> {
+ let r = 0xD;
+ }
+
+ def PITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "pitlb\t$t, $s", []> {
+ let r = 0x5;
+ }
+
+ def RDTLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "rdtlb0\t$t, $s", []> {
+ let r = 0xB;
+ }
+
+ def RDTLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "rdtlb1\t$t, $s", []> {
+ let r = 0xF;
+ }
+
+ def RITLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "ritlb0\t$t, $s", []> {
+ let r = 0x3;
+ }
+
+ def RITLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "ritlb1\t$t, $s", []> {
+ let r = 0x7;
+ }
+
+ def WDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "wdtlb\t$t, $s", []> {
+ let r = 0xE;
+ }
+
+ def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "witlb\t$t, $s", []> {
+ let r = 0x6;
+ }
+}
+
//===----------------------------------------------------------------------===//
// DSP Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
index 2a40431adc7f0..c54e2556ba11f 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
@@ -84,10 +84,25 @@ def SAR : SRReg<3, "sar", ["SAR","3"]>;
// Boolean Register
def BREG : SRReg<4, "br", ["BR","4"]>;
+// Literal base
+def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>;
+
// Windowed Register Option registers
def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>;
def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>;
+// Memory Control Register
+def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>;
+
+// Vector base register
+def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>;
+
+// Xtensa Miscellaneous SR
+def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>;
+def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>;
+def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>;
+def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>;
+
// MAC16 Option registers
def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>;
def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>;
@@ -101,7 +116,8 @@ def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
def SR : RegisterClass<"Xtensa", [i32], 32, (add
- LBEG, LEND, LCOUNT, SAR, BREG, MR, WINDOWBASE, WINDOWSTART)>;
+ LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART,
+ MEMCTL, VECBASE, MISC0, MISC1, MISC2, MISC3)>;
//===----------------------------------------------------------------------===//
// Boolean registers
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index 227ce2134b33b..9909fb9ff4b37 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -77,6 +77,11 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
bool hasMul32() const { return HasMul32; }
bool hasMul32High() const { return HasMul32High; }
bool hasDiv32() const { return HasDiv32; }
+ bool hasRegionProtection() const { return HasRegionProtection; }
+ bool hasRelocatableVector() const { return HasRelocatableVector; }
+ bool hasMiscSR() const { return HasMiscSR; }
+ bool hasExtendedL32R() const { return HasExtendedL32R; }
+ bool hasDataCache() const { return HasDataCache; }
bool isWindowedABI() const { return hasWindowed(); }
// Automatically generated by tblgen.
diff --git a/llvm/test/MC/Disassembler/Xtensa/clamps.txt b/llvm/test/MC/Disassembler/Xtensa/clamps.txt
new file mode 100644
index 0000000000000..bb6912d99f6c6
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/clamps.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+clamps -disassemble %s | FileCheck -check-prefixes=CHECK-CLAMPS %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## clamps option enabled. Also verify that dissasembling without
+## clamps option generates warnings.
+
+[0x00,0x34,0x33]
+# CHECK-CLAMPS: clamps a3, a4, 7
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/code_density.txt b/llvm/test/MC/Disassembler/Xtensa/code_density.txt
index 833dd52e584b2..9a92eb7068a02 100644
--- a/llvm/test/MC/Disassembler/Xtensa/code_density.txt
+++ b/llvm/test/MC/Disassembler/Xtensa/code_density.txt
@@ -1,11 +1,9 @@
# RUN: llvm-mc -triple=xtensa -mattr=+density -disassemble %s | FileCheck -check-prefixes=CHECK-DENSITY %s
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
-#------------------------------------------------------------------------------
-# Verify that binary code is correctly disassembled with
-# code density option enabled. Also verify that dissasembling without
-# density option generates warnings.
-#------------------------------------------------------------------------------
+## Verify that binary code is correctly disassembled with
+## code density option enabled. Also verify that dissasembling without
+## density option generates warnings.
[0x4a, 0x23]
# CHECK-DENSITY: add.n a2, a3, a4
diff --git a/llvm/test/MC/Disassembler/Xtensa/dcache.txt b/llvm/test/MC/Disassembler/Xtensa/dcache.txt
new file mode 100644
index 0000000000000..66aac95885f67
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/dcache.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+dcache -disassemble %s | FileCheck -check-prefixes=CHECK-DCACHE %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## dcache option enabled. Also verify that dissasembling without
+## dcache option generates warnings.
+
+[0x30,0x61,0x61]
+# CHECK-DCACHE: xsr a3, memctl
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/div.txt b/llvm/test/MC/Disassembler/Xtensa/div.txt
new file mode 100644
index 0000000000000..812cfcd7de653
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/div.txt
@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+div32 -disassemble %s | FileCheck -check-prefixes=CHECK-DIV32 %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## div32 option enabled. Also verify that dissasembling without
+## div32 option generates warnings.
+
+[0x50,0x34,0xd2]
+# CHECK-DIV32: quos a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0xc2]
+# CHECK-DIV32: quou a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0xf2]
+# CHECK-DIV32: rems a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0xe2]
+# CHECK-DIV32: remu a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/extendedl32r.txt b/llvm/test/MC/Disassembler/Xtensa/extendedl32r.txt
new file mode 100644
index 0000000000000..ecc2786497f88
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/extendedl32r.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+extendedl32r -disassemble %s | FileCheck -check-prefixes=CHECK-EXTENDEDL32R %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## extendedl32r option enabled. Also verify that dissasembling without
+## extendedl32r option generates warnings.
+
+[0x30,0x05,0x61]
+# CHECK-EXTENDEDL32R: xsr a3, litbase
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/loop.txt b/llvm/test/MC/Disassembler/Xtensa/loop.txt
new file mode 100644
index 0000000000000..3e611b32b6dc6
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/loop.txt
@@ -0,0 +1,30 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+loop -disassemble %s | FileCheck -check-prefixes=CHECK-LOOP %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## loop option enabled. Also verify that dissasembling without
+## loop option generates warnings.
+
+[0x76,0x83,0x40]
+# CHECK-LOOP: loop a3, . +68
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x76,0x93,0x40]
+# CHECK-LOOP: loopnez a3, . +68
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x76,0xa3,0x40]
+# CHECK-LOOP: loopgtz a3, . +68
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x00,0x61]
+# CHECK-LOOP: xsr a3, lbeg
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x01,0x61]
+# CHECK-LOOP: xsr a3, lend
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x02,0x61]
+# CHECK-LOOP: xsr a3, lcount
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/mac16.txt b/llvm/test/MC/Disassembler/Xtensa/mac16.txt
new file mode 100644
index 0000000000000..156261d7a32ee
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/mac16.txt
@@ -0,0 +1,310 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+mac16 -disassemble %s | FileCheck -check-prefixes=CHECK-MAC16 %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## mac16 option enabled. Also verify that dissasembling without
+## mac16 option generates warnings.
+
+[0x34,0x02,0x70]
+# CHECK-MAC16: umul.aa.ll a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x72]
+# CHECK-MAC16: umul.aa.lh a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x71]
+# CHECK-MAC16: umul.aa.hl a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x73]
+# CHECK-MAC16: umul.aa.hh a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x74]
+# CHECK-MAC16: mul.aa.ll a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x76]
+# CHECK-MAC16: mul.aa.lh a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x75]
+# CHECK-MAC16: mul.aa.hl a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x77]
+# CHECK-MAC16: mul.aa.hh a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x34]
+# CHECK-MAC16: mul.ad.ll a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x36]
+# CHECK-MAC16: mul.ad.lh a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x35]
+# CHECK-MAC16: mul.ad.hl a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x37]
+# CHECK-MAC16: mul.ad.hh a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x64]
+# CHECK-MAC16: mul.da.ll m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x66]
+# CHECK-MAC16: mul.da.lh m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x65]
+# CHECK-MAC16: mul.da.hl m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x67]
+# CHECK-MAC16: mul.da.hh m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x24]
+# CHECK-MAC16: mul.dd.ll m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x26]
+# CHECK-MAC16: mul.dd.lh m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x25]
+# CHECK-MAC16: mul.dd.hl m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x27]
+# CHECK-MAC16: mul.dd.hh m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x78]
+# CHECK-MAC16: mula.aa.ll a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x7a]
+# CHECK-MAC16: mula.aa.lh a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x79]
+# CHECK-MAC16: mula.aa.hl a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x7b]
+# CHECK-MAC16: mula.aa.hh a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x38]
+# CHECK-MAC16: mula.ad.ll a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x3a]
+# CHECK-MAC16: mula.ad.lh a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x39]
+# CHECK-MAC16: mula.ad.hl a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x3b]
+# CHECK-MAC16: mula.ad.hh a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x68]
+# CHECK-MAC16: mula.da.ll m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x6a]
+# CHECK-MAC16: mula.da.lh m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x69]
+# CHECK-MAC16: mula.da.hl m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x6b]
+# CHECK-MAC16: mula.da.hh m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x28]
+# CHECK-MAC16: mula.dd.ll m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x2a]
+# CHECK-MAC16: mula.dd.lh m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x29]
+# CHECK-MAC16: mula.dd.hl m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x2b]
+# CHECK-MAC16: mula.dd.hh m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x7c]
+# CHECK-MAC16: muls.aa.ll a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x7e]
+# CHECK-MAC16: muls.aa.lh a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x7d]
+# CHECK-MAC16: muls.aa.hl a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x02,0x7f]
+# CHECK-MAC16: muls.aa.hh a2, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x3c]
+# CHECK-MAC16: muls.ad.ll a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x3e]
+# CHECK-MAC16: muls.ad.lh a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x3d]
+# CHECK-MAC16: muls.ad.hl a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x02,0x3f]
+# CHECK-MAC16: muls.ad.hh a2, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x6c]
+# CHECK-MAC16: muls.da.ll m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x6e]
+# CHECK-MAC16: muls.da.lh m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x6d]
+# CHECK-MAC16: muls.da.hl m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x40,0x6f]
+# CHECK-MAC16: muls.da.hh m1, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x2c]
+# CHECK-MAC16: muls.dd.ll m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x2e]
+# CHECK-MAC16: muls.dd.lh m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x2d]
+# CHECK-MAC16: muls.dd.hl m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x40,0x2f]
+# CHECK-MAC16: muls.dd.hh m1, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x18,0x58]
+# CHECK-MAC16: mula.da.ll.lddec m1, a8, m0, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x18,0x59]
+# CHECK-MAC16: mula.da.hl.lddec m1, a8, m0, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x18,0x5a]
+# CHECK-MAC16: mula.da.lh.lddec m1, a8, m0, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x18,0x5b]
+# CHECK-MAC16: mula.da.hh.lddec m1, a8, m0, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x18,0x18]
+# CHECK-MAC16: mula.dd.ll.lddec m1, a8, m0, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x18,0x19]
+# CHECK-MAC16: mula.dd.hl.lddec m1, a8, m0, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x18,0x1a]
+# CHECK-MAC16: mula.dd.lh.lddec m1, a8, m0, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x18,0x1b]
+# CHECK-MAC16: mula.dd.hh.lddec m1, a8, m0, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x18,0x48]
+# CHECK-MAC16: mula.da.ll.ldinc m1, a8, m0, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x18,0x49]
+# CHECK-MAC16: mula.da.hl.ldinc m1, a8, m0, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x18,0x4a]
+# CHECK-MAC16: mula.da.lh.ldinc m1, a8, m0, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x34,0x18,0x4b]
+# CHECK-MAC16: mula.da.hh.ldinc m1, a8, m0, a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x18,0x08]
+# CHECK-MAC16: mula.dd.ll.ldinc m1, a8, m0, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x18,0x09]
+# CHECK-MAC16: mula.dd.hl.ldinc m1, a8, m0, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x18,0x0a]
+# CHECK-MAC16: mula.dd.lh.ldinc m1, a8, m0, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x18,0x0b]
+# CHECK-MAC16: mula.dd.hh.ldinc m1, a8, m0, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x08,0x90]
+# CHECK-MAC16: lddec m0, a8
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x04,0x08,0x80]
+# CHECK-MAC16: ldinc m0, a8
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x10,0x61]
+# CHECK-MAC16: xsr a3, acclo
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x11,0x61]
+# CHECK-MAC16: xsr a3, acchi
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x20,0x61]
+# CHECK-MAC16: xsr a3, m0
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x21,0x61]
+# CHECK-MAC16: xsr a3, m1
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x22,0x61]
+# CHECK-MAC16: xsr a3, m2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x23,0x61]
+# CHECK-MAC16: xsr a3, m3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/minmax.txt b/llvm/test/MC/Disassembler/Xtensa/minmax.txt
new file mode 100644
index 0000000000000..9e5af98e02fe3
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/minmax.txt
@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+minmax -disassemble %s | FileCheck -check-prefixes=CHECK-MINMAX %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## minmax option enabled. Also verify that dissasembling without
+## minmax option generates warnings.
+
+[0x50,0x34,0x53]
+# CHECK-MINMAX: max a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0x73]
+# CHECK-MINMAX: maxu a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0x43]
+# CHECK-MINMAX: min a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0x63]
+# CHECK-MINMAX: minu a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/miscsr.txt b/llvm/test/MC/Disassembler/Xtensa/miscsr.txt
new file mode 100644
index 0000000000000..49919e86de850
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/miscsr.txt
@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+miscsr -disassemble %s | FileCheck -check-prefixes=CHECK-MISCSR %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## miscr option enabled. Also verify that dissasembling without
+## miscr option generates warnings.
+
+[0x30,0xf4,0x61]
+# CHECK-MISCSR: xsr a3, misc0
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0xf5,0x61]
+# CHECK-MISCSR: xsr a3, misc1
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0xf6,0x61]
+# CHECK-MISCSR: xsr a3, misc2
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0xf7,0x61]
+# CHECK-MISCSR: xsr a3, misc3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/mul.txt b/llvm/test/MC/Disassembler/Xtensa/mul.txt
new file mode 100644
index 0000000000000..b251d22cdfda6
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/mul.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+mul32 -disassemble %s | FileCheck -check-prefixes=CHECK-MUL32 %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## mul32 option enabled. Also verify that dissasembling without
+## mul32 option generates warnings.
+
+[0x50,0x34,0x82]
+# CHECK-MUL32: mull a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/mul16.txt b/llvm/test/MC/Disassembler/Xtensa/mul16.txt
new file mode 100644
index 0000000000000..c10a3b6b46521
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/mul16.txt
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+mul16 -disassemble %s | FileCheck -check-prefixes=CHECK-MUL16 %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## mul16 option enabled. Also verify that dissasembling without
+## mul16 option generates warnings.
+
+[0x50,0x34,0xd1]
+# CHECK-MUL16: mul16s a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0xc1]
+# CHECK-MUL16: mul16u a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/mul32high.txt b/llvm/test/MC/Disassembler/Xtensa/mul32high.txt
new file mode 100644
index 0000000000000..b0a393e6506ea
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/mul32high.txt
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+mul32high -disassemble %s | FileCheck -check-prefixes=CHECK-MUL32HIGH %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## mul32high option enabled. Also verify that dissasembling without
+## mul32high option generates warnings.
+
+[0x50,0x34,0xa2]
+# CHECK-MUL32HIGH: muluh a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0xb2]
+# CHECK-MUL32HIGH: mulsh a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/nsa.txt b/llvm/test/MC/Disassembler/Xtensa/nsa.txt
new file mode 100644
index 0000000000000..9186f5e6adec5
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/nsa.txt
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+nsa -disassemble %s | FileCheck -check-prefixes=CHECK-NSA %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## nsa option enabled. Also verify that dissasembling without
+## nsa option generates warnings.
+
+[0x30,0xe4,0x40]
+# CHECK-NSA: nsa a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0xf4,0x40]
+# CHECK-NSA: nsau a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/region_protect.txt b/llvm/test/MC/Disassembler/Xtensa/region_protect.txt
new file mode 100644
index 0000000000000..b486a21a711b0
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/region_protect.txt
@@ -0,0 +1,46 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+regprotect -disassemble %s | FileCheck -check-prefixes=CHECK-REGPROTECT %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## region protection option enabled. Also verify that dissasembling without
+## region protection option generates warnings.
+
+[0x00,0xc3,0x50]
+# CHECK-REGPROTECT: idtlb a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x00,0x43,0x50]
+# CHECK-REGPROTECT: iitlb a3
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0xd4,0x50]
+# CHECK-REGPROTECT: pdtlb a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x54,0x50]
+# CHECK-REGPROTECT: pitlb a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0xb4,0x50]
+# CHECK-REGPROTECT: rdtlb0 a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0xf4,0x50]
+# CHECK-REGPROTECT: rdtlb1 a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x34,0x50]
+# CHECK-REGPROTECT: ritlb0 a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x74,0x50]
+# CHECK-REGPROTECT: ritlb1 a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0xe4,0x50]
+# CHECK-REGPROTECT: wdtlb a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x64,0x50]
+# CHECK-REGPROTECT: witlb a3, a4
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/rvector.txt b/llvm/test/MC/Disassembler/Xtensa/rvector.txt
new file mode 100644
index 0000000000000..c2a0ca3e43f39
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/rvector.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+rvector -disassemble %s | FileCheck -check-prefixes=CHECK-RVECTOR %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## rvector option enabled. Also verify that dissasembling without
+## rvector option generates warnings.
+
+[0x30,0xe7,0x61]
+# CHECK-RVECTOR: xsr a3, vecbase
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/Xtensa/sext.txt b/llvm/test/MC/Disassembler/Xtensa/sext.txt
new file mode 100644
index 0000000000000..cb702f3c0d70b
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Xtensa/sext.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+sext -disassemble %s | FileCheck -check-prefixes=CHECK-SEXT %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## sext option enabled. Also verify that dissasembling without
+## sext option generates warnings.
+
+[0x00,0x34,0x23]
+# CHECK-SEXT: sext a3, a4, 7
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Xtensa/clamps-invalid.s b/llvm/test/MC/Xtensa/clamps-invalid.s
new file mode 100644
index 0000000000000..cc09dddfcd6ae
--- /dev/null
+++ b/llvm/test/MC/Xtensa/clamps-invalid.s
@@ -0,0 +1,9 @@
+# RUN: not llvm-mc -triple xtensa --mattr=+clamps %s 2>&1 | FileCheck %s
+
+.align 4
+
+# Out of range immediates
+
+# imm7_22
+clamps a3, a4, 5
+# CHECK: :[[#@LINE-1]]:16: error: expected immediate in range [7, 22]
diff --git a/llvm/test/MC/Xtensa/clamps.s b/llvm/test/MC/Xtensa/clamps.s
new file mode 100644
index 0000000000000..79737b127c760
--- /dev/null
+++ b/llvm/test/MC/Xtensa/clamps.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+clamps \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RRR
+# CHECK-INST: clamps a3, a4, 7
+# CHECK: encoding: [0x00,0x34,0x33]
+clamps a3, a4, 7
diff --git a/llvm/test/MC/Xtensa/dcache.s b/llvm/test/MC/Xtensa/dcache.s
new file mode 100644
index 0000000000000..9baa4980a6107
--- /dev/null
+++ b/llvm/test/MC/Xtensa/dcache.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+dcache \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, memctl
+# CHECK: # encoding: [0x30,0x61,0x61]
+xsr a3, memctl
+
+# CHECK-INST: xsr a3, memctl
+# CHECK: # encoding: [0x30,0x61,0x61]
+xsr.memctl a3
+
+# CHECK-INST: xsr a3, memctl
+# CHECK: # encoding: [0x30,0x61,0x61]
+xsr a3, 97
diff --git a/llvm/test/MC/Xtensa/extendedl32r.s b/llvm/test/MC/Xtensa/extendedl32r.s
new file mode 100644
index 0000000000000..d13a6b751b0dc
--- /dev/null
+++ b/llvm/test/MC/Xtensa/extendedl32r.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+extendedl32r \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, litbase
+# CHECK: # encoding: [0x30,0x05,0x61]
+xsr a3, litbase
+
+# CHECK-INST: xsr a3, litbase
+# CHECK: # encoding: [0x30,0x05,0x61]
+xsr.litbase a3
+
+# CHECK-INST: xsr a3, litbase
+# CHECK: # encoding: [0x30,0x05,0x61]
+xsr a3, 5
diff --git a/llvm/test/MC/Xtensa/miscsr.s b/llvm/test/MC/Xtensa/miscsr.s
new file mode 100644
index 0000000000000..82954dfde19f2
--- /dev/null
+++ b/llvm/test/MC/Xtensa/miscsr.s
@@ -0,0 +1,56 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+miscsr \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, misc0
+# CHECK: # encoding: [0x30,0xf4,0x61]
+xsr a3, misc0
+
+# CHECK-INST: xsr a3, misc0
+# CHECK: # encoding: [0x30,0xf4,0x61]
+xsr.misc0 a3
+
+# CHECK-INST: xsr a3, misc0
+# CHECK: # encoding: [0x30,0xf4,0x61]
+xsr a3, 244
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, misc1
+# CHECK: # encoding: [0x30,0xf5,0x61]
+xsr a3, misc1
+
+# CHECK-INST: xsr a3, misc1
+# CHECK: # encoding: [0x30,0xf5,0x61]
+xsr.misc1 a3
+
+# CHECK-INST: xsr a3, misc1
+# CHECK: # encoding: [0x30,0xf5,0x61]
+xsr a3, 245
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, misc2
+# CHECK: # encoding: [0x30,0xf6,0x61]
+xsr a3, misc2
+
+# CHECK-INST: xsr a3, misc2
+# CHECK: # encoding: [0x30,0xf6,0x61]
+xsr.misc2 a3
+
+# CHECK-INST: xsr a3, misc2
+# CHECK: # encoding: [0x30,0xf6,0x61]
+xsr a3, 246
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, misc3
+# CHECK: # encoding: [0x30,0xf7,0x61]
+xsr a3, misc3
+
+# CHECK-INST: xsr a3, misc3
+# CHECK: # encoding: [0x30,0xf7,0x61]
+xsr.misc3 a3
+
+# CHECK-INST: xsr a3, misc3
+# CHECK: # encoding: [0x30,0xf7,0x61]
+xsr a3, 247
diff --git a/llvm/test/MC/Xtensa/region_protect.s b/llvm/test/MC/Xtensa/region_protect.s
new file mode 100644
index 0000000000000..dfe30e93972b2
--- /dev/null
+++ b/llvm/test/MC/Xtensa/region_protect.s
@@ -0,0 +1,54 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+regprotect \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RRR
+# CHECK-INST: idtlb a3
+# CHECK: encoding: [0x00,0xc3,0x50]
+idtlb a3
+
+# Instruction format RRR
+# CHECK-INST: iitlb a3
+# CHECK: encoding: [0x00,0x43,0x50]
+iitlb a3
+
+# Instruction format RRR
+# CHECK-INST: pdtlb a3, a4
+# CHECK: encoding: [0x30,0xd4,0x50]
+pdtlb a3, a4
+
+# Instruction format RRR
+# CHECK-INST: pitlb a3, a4
+# CHECK: encoding: [0x30,0x54,0x50]
+pitlb a3, a4
+
+# Instruction format RRR
+# CHECK-INST: rdtlb0 a3, a4
+# CHECK: encoding: [0x30,0xb4,0x50]
+rdtlb0 a3, a4
+
+# Instruction format RRR
+# CHECK-INST: rdtlb1 a3, a4
+# CHECK: encoding: [0x30,0xf4,0x50]
+rdtlb1 a3, a4
+
+# Instruction format RRR
+# CHECK-INST: ritlb0 a3, a4
+# CHECK: encoding: [0x30,0x34,0x50]
+ritlb0 a3, a4
+
+# Instruction format RRR
+# CHECK-INST: ritlb1 a3, a4
+# CHECK: encoding: [0x30,0x74,0x50]
+ritlb1 a3, a4
+
+# Instruction format RRR
+# CHECK-INST: wdtlb a3, a4
+# CHECK: encoding: [0x30,0xe4,0x50]
+wdtlb a3, a4
+
+# Instruction format RRR
+# CHECK-INST: witlb a3, a4
+# CHECK: encoding: [0x30,0x64,0x50]
+witlb a3, a4
diff --git a/llvm/test/MC/Xtensa/rvector.s b/llvm/test/MC/Xtensa/rvector.s
new file mode 100644
index 0000000000000..17481cc8b35d3
--- /dev/null
+++ b/llvm/test/MC/Xtensa/rvector.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+rvector \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, vecbase
+# CHECK: # encoding: [0x30,0xe7,0x61]
+xsr a3, vecbase
+
+# CHECK-INST: xsr a3, vecbase
+# CHECK: # encoding: [0x30,0xe7,0x61]
+xsr.vecbase a3
+
+# CHECK-INST: xsr a3, vecbase
+# CHECK: # encoding: [0x30,0xe7,0x61]
+xsr a3, 231
diff --git a/llvm/test/MC/Xtensa/xtensa-mac16.s b/llvm/test/MC/Xtensa/xtensa-mac16.s
index 15200751ec8a0..fff4cbf639856 100644
--- a/llvm/test/MC/Xtensa/xtensa-mac16.s
+++ b/llvm/test/MC/Xtensa/xtensa-mac16.s
@@ -231,3 +231,76 @@ LBL0:
# CHECK-INST: ldinc m0, a8
# CHECK: encoding: [0x04,0x08,0x80]
ldinc m0, a8
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, acclo
+# CHECK: # encoding: [0x30,0x10,0x61]
+xsr a3, acclo
+
+# CHECK-INST: xsr a3, acclo
+# CHECK: # encoding: [0x30,0x10,0x61]
+xsr.acclo a3
+
+# CHECK-INST: xsr a3, acclo
+# CHECK: # encoding: [0x30,0x10,0x61]
+xsr a3, 16
+
+# CHECK-INST: xsr a3, acchi
+# CHECK: # encoding: [0x30,0x11,0x61]
+xsr a3, acchi
+
+# CHECK-INST: xsr a3, acchi
+# CHECK: # encoding: [0x30,0x11,0x61]
+xsr.acchi a3
+
+# CHECK-INST: xsr a3, acchi
+# CHECK: # encoding: [0x30,0x11,0x61]
+xsr a3, 17
+
+# CHECK-INST: xsr a3, m0
+# CHECK: # encoding: [0x30,0x20,0x61]
+xsr a3, m0
+
+# CHECK-INST: xsr a3, m0
+# CHECK: # encoding: [0x30,0x20,0x61]
+xsr.m0 a3
+
+# CHECK-INST: xsr a3, m0
+# CHECK: # encoding: [0x30,0x20,0x61]
+xsr a3, 32
+
+# CHECK-INST: xsr a3, m1
+# CHECK: # encoding: [0x30,0x21,0x61]
+xsr a3, m1
+
+# CHECK-INST: xsr a3, m1
+# CHECK: # encoding: [0x30,0x21,0x61]
+xsr.m1 a3
+
+# CHECK-INST: xsr a3, m1
+# CHECK: # encoding: [0x30,0x21,0x61]
+xsr a3, 33
+
+# CHECK-INST: xsr a3, m2
+# CHECK: # encoding: [0x30,0x22,0x61]
+xsr a3, m2
+
+# CHECK-INST: xsr a3, m2
+# CHECK: # encoding: [0x30,0x22,0x61]
+xsr.m2 a3
+
+# CHECK-INST: xsr a3, m2
+# CHECK: # encoding: [0x30,0x22,0x61]
+xsr a3, 34
+
+# CHECK-INST: xsr a3, m3
+# CHECK: # encoding: [0x30,0x23,0x61]
+xsr a3, m3
+
+# CHECK-INST: xsr a3, m3
+# CHECK: # encoding: [0x30,0x23,0x61]
+xsr.m3 a3
+
+# CHECK-INST: xsr a3, m3
+# CHECK: # encoding: [0x30,0x23,0x61]
+xsr a3, 35
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