[llvm] [RISCV][FPEnv] Lowering of fpenv intrinsics (PR #141498)

[Serge Pavlov via llvm-commits]

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@@ -2028,6 +2028,11 @@ let hasSideEffects = true in {
 def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>;
 def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>;
 }
+
+def ReadFCSR : ReadSysReg<SysRegFCSR, [FRM, FFLAGS]>;
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spavloff wrote:

It looks like too rigid restriction. ReadFFLAGS and WriteFFLAGS already have FRM and FFLAGS as inplicit use/def, shouldn't that be sufficient to provide the necessary ordering?

https://github.com/llvm/llvm-project/pull/141498