[llvm] [RISCV] Add BREV8 to SimplifyDemandedBitsForTargetNode. (PR #141898)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed May 28 23:13:03 PDT 2025
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/141898
None
>From d80609c55947cc78185da10046c67f21addb007e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 28 May 2025 23:08:46 -0700
Subject: [PATCH] [RISCV] Add BREV8 to SimplifyDemandedBitsForTargetNode.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 32 +++++++++++++++++++--
llvm/lib/Target/RISCV/RISCVISelLowering.h | 6 ++++
llvm/test/CodeGen/RISCV/bswap-bitreverse.ll | 4 +--
3 files changed, 38 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0a849f49116ee..f6cdd0d30aaf7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20575,8 +20575,7 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
bool IsGORC = Op.getOpcode() == RISCVISD::ORC_B;
// To compute zeros, we need to invert the value and invert it back after.
- Known.Zero =
- ~computeGREVOrGORC(~Known.Zero.getZExtValue(), 7, IsGORC);
+ Known.Zero = ~computeGREVOrGORC(~Known.Zero.getZExtValue(), 7, IsGORC);
Known.One = computeGREVOrGORC(Known.One.getZExtValue(), 7, IsGORC);
break;
}
@@ -20717,6 +20716,35 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
return 1;
}
+bool RISCVTargetLowering::SimplifyDemandedBitsForTargetNode(
+ SDValue Op, const APInt &OriginalDemandedBits,
+ const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO,
+ unsigned Depth) const {
+ unsigned BitWidth = OriginalDemandedBits.getBitWidth();
+
+ switch (Op.getOpcode()) {
+ case RISCVISD::BREV8: {
+ KnownBits Known2;
+ APInt DemandedBits =
+ APInt(BitWidth, computeGREVOrGORC(OriginalDemandedBits.getZExtValue(),
+ 7, /*IsGORC=*/false));
+ if (SimplifyDemandedBits(Op.getOperand(0), DemandedBits,
+ OriginalDemandedElts, Known2, TLO, Depth + 1))
+ return true;
+
+ // To compute zeros, we need to invert the value and invert it back after.
+ Known.Zero =
+ ~computeGREVOrGORC(~Known2.Zero.getZExtValue(), 7, /*IsGORC=*/false);
+ Known.One =
+ computeGREVOrGORC(Known2.One.getZExtValue(), 7, /*IsGORC=*/false);
+ return false;
+ }
+ }
+
+ return TargetLowering::SimplifyDemandedBitsForTargetNode(
+ Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
+}
+
bool RISCVTargetLowering::canCreateUndefOrPoisonForTargetNode(
SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 78f2044ba83a7..ed27e1ea5ef6d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -153,6 +153,12 @@ class RISCVTargetLowering : public TargetLowering {
const SelectionDAG &DAG,
unsigned Depth) const override;
+ bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits,
+ const APInt &DemandedElts,
+ KnownBits &Known,
+ TargetLoweringOpt &TLO,
+ unsigned Depth) const override;
+
bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
const APInt &DemandedElts,
const SelectionDAG &DAG,
diff --git a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
index 40a5772142345..1afb03b346a1a 100644
--- a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
@@ -245,14 +245,14 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind {
;
; RV32ZBKB-LABEL: test_bitreverse_i8:
; RV32ZBKB: # %bb.0:
-; RV32ZBKB-NEXT: rev8 a0, a0
+; RV32ZBKB-NEXT: slli a0, a0, 24
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 24
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_i8:
; RV64ZBKB: # %bb.0:
-; RV64ZBKB-NEXT: rev8 a0, a0
+; RV64ZBKB-NEXT: slli a0, a0, 56
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 56
; RV64ZBKB-NEXT: ret
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