[llvm] [RISCV] Add BREV8 to isSignExtendedW in RISCVOptWInstrs. (PR #141893)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed May 28 21:50:14 PDT 2025


topperc wrote:

This patch is invalid. We still need to know that bit 31 matches.

https://github.com/llvm/llvm-project/pull/141893


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